Datasheet

XIO2213B
www.ti.com SCPS210F –OCTOBER 2008–REVISED MAY 2013
7.21 PCI Miscellaneous Configuration Register ........................................................................... 125
7.22 Link Enhancement Control Register ................................................................................... 128
7.23 Subsystem Access Register ............................................................................................ 130
8 1394 OHCI Memory-Mapped Register Space ....................................................................... 131
8.1 OHCI Version Register .................................................................................................. 134
8.2 GUID ROM Register ..................................................................................................... 135
8.3 Asynchronous Transmit Retries Register ............................................................................. 136
8.4 CSR Data Register ...................................................................................................... 136
8.5 CSR Compare Register ................................................................................................. 137
8.6 CSR Control Register ................................................................................................... 137
8.7 Configuration ROM Header Register .................................................................................. 138
8.8 Bus Identification Register .............................................................................................. 138
8.9 Bus Options Register .................................................................................................... 139
8.10 GUID High Register ..................................................................................................... 140
8.11 GUID Low Register ...................................................................................................... 140
8.12 Configuration ROM Mapping Register ................................................................................ 141
8.13 Posted Write Address Low Register ................................................................................... 141
8.14 Posted Write Address High Register .................................................................................. 142
8.15 Vendor ID Register ...................................................................................................... 142
8.16 Host Controller Control Register ....................................................................................... 142
8.17 Self-ID Buffer Pointer Register ......................................................................................... 145
8.18 Self-ID Count Register .................................................................................................. 145
8.19 Isochronous Receive Channel Mask High Register ................................................................. 146
8.20 Isochronous Receive Channel Mask Low Register ................................................................. 148
8.21 Interrupt Event Register ................................................................................................. 148
8.22 Interrupt Mask Register ................................................................................................. 150
8.23 Isochronous Transmit Interrupt Event Register ...................................................................... 152
8.24 Isochronous Transmit Interrupt Mask Register ...................................................................... 153
8.25 Isochronous Receive Interrupt Event Register ....................................................................... 153
8.26 Isochronous Receive Interrupt Mask Register ....................................................................... 154
8.27 Initial Bandwidth Available Register ................................................................................... 154
8.28 Initial Channels Available High Register .............................................................................. 155
8.29 Initial Channels Available Low Register .............................................................................. 155
8.30 Fairness Control Register ............................................................................................... 156
8.31 Link Control Register .................................................................................................... 157
8.32 Node Identification Register ............................................................................................ 158
8.33 PHY Control Register ................................................................................................... 159
8.34 Isochronous Cycle Timer Register ..................................................................................... 160
8.35 Asynchronous Request Filter High Register ......................................................................... 160
8.36 Asynchronous Request Filter Low Register .......................................................................... 163
8.37 Physical Request Filter High Register ................................................................................ 163
8.38 Physical Request Filter Low Register ................................................................................. 166
8.39 Physical Upper Bound Register (Optional Register) ................................................................ 166
8.40 Asynchronous Context Control Register .............................................................................. 167
8.41 Asynchronous Context Command Pointer Register ................................................................. 168
8.42 Isochronous Transmit Context Control Register ..................................................................... 169
8.43 Isochronous Transmit Context Command Pointer Register ........................................................ 170
8.44 Isochronous Receive Context Control Register ...................................................................... 170
8.45 Isochronous Receive Context Command Pointer Register ......................................................... 172
8.46 Isochronous Receive Context Match Register ....................................................................... 172
9 1394 OHCI Memory-Mapped TI Extension Register Space ..................................................... 174
9.1 Digital Video (DV) and MPEG2 Timestamp Enhancements ....................................................... 174
9.2 Isochronous Receive Digital Video Enhancements ................................................................. 175
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