Datasheet

XIO2213B
SCPS210F –OCTOBER 2008–REVISED MAY 2013 www.ti.com
4 Classic PCI Configuration Space
The programming model of the XIO2213B PCIe to PCI bridge is compliant to the classic PCI-to-PCI bridge
programming model. The PCI configuration map uses the type 1 PCI bridge header.
Sticky bits are reset by a global reset (GRST) or the internally-generated power-on reset. EEPROM
loadable bits are reset by a PCIe reset (PERST), GRST, or the internally-generated power-on reset. The
remaining register bits are reset by a PCIe hot reset, PERST, GRST, or the internally-generated power-on
reset.
Table 4-1. Classic PCI Configuration Register Map
REGISTER NAME OFFSET
Device ID Vendor ID 000h
Status Command 004h
Class code Revision ID 008h
BIST Header type Primary latency timer Cache line size 00Ch
Device contol base address 010h
Scratchpad RAM base address 014h
Secondary latency timer Subordinate bus number Secondary bus number Primary bus number 018h
Secondary status I/O limit I/O base 01Ch
Memory limit Memory base 020h
Prefetchable memory limit Prefetchable memory base 024h
Prefetchable base upper 32 bits 028h
Prefetchable limit upper 32 bits 02Ch
I/O limit upper 16 bits I/O base upper 16 bits 030h
Reserved Capabilities pointer 034h
Reserved 038h
Bridge control Interrupt pin Interrupt line 03Ch
Reserved 040h-04Ch
Power management capabilities Next item pointer PM apability ID 050h
Power management bridge
Power management data Power management control/status 054h
support extention
Reserved 058h-05Ch
MSI message control Next item pointer MSI capability ID 060h
MSI message lower address 064h
MSI message upper address 068h
Reserved MSI message data 06Ch
Reserved 070h-07Ch
Reserved Next item pointer SSID/SSVID capability ID 080h
Subsystem ID
(1)
Subsystem vendor ID
(1)
084h
Reserved 088h-08Ch
PCI Express capabilities register Next item pointer PCI Express capability ID 090h
Device capabilities 094h
Device status Device control 098h
Link capabilities 09Ch
Link status Link control 0A0h
Reserved 0A4h-0ACh
Serial-bus control and
Serial-bus slave address
(1)
Serial-bus word address
(1)
Serial-bus data
(1)
0B0h
status
(1)
GPIO data
(1)
GPIO control
(1)
0B4h
(1) One or more bits in this register are reset by PERST, GRST, or the internally-generated power-on reset.
48 Classic PCI Configuration Space Copyright © 2008–2013, Texas Instruments Incorporated
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