Datasheet

XIO2213B
SCPS210F OCTOBER 2008REVISED MAY 2013
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3.11 1394b OHCI Controller Functionality
3.11.1 1394b OHCI Power Management
The 1394b OHCI controller complies with the PCI Bus Power Management Interface Specification. The
controller supports the D0 (uninitialized), D0 (active), D1, D2, and D3 power states as defined by the
power-management definition in the 1394 Open Host Controller Interface Specification, Appendix A4.
Table 3-7 identifies the supported power-management registers within the 1394 OHCI configuration
register map.
Table 3-7. 1394b OHCI Configuration Register Map
REGISTER NAME OFFSET
Power management capabilities Next item pointer Capability ID 44h
PM data Power management control/status register bridge support extensions Power management control/status (CSR) 48h
3.11.2 1394b OHCI and V
AUX
The 1394b OHCI function within the XIO2213B is powered by V
DD_MAIN
only. Therefore, during the D3
cold
power-management state, V
AUX
is not supplied to the 1394b OHCI function.
This implies that the 1394b OHCI function does not implement sticky bits must be initialized after a D3
cold
power-management state. An external serial EEPROM interface is available to initialize critical
configuration register bits. The EEPROM download is triggered by the deassertion of the PERST input.
Otherwise, the BIOS must initialize the 1394b OHCI function.
3.11.3 1394b OHCI and Reset Options
The 1394b OHCI function is completely reset by the internal power-on reset feature, GRST input, or
PERST input. This includes all EEPROM loadable bits, power-management functions, and all remaining
configuration register bits and logic.
A PCIe training control hot reset or the PCI bus configuration register reset bit (SRST) excludes the
EEPROM loadable bits, power-management functions, and 1394 PHY. All remaining configuration
registers and logic are reset.
If the OHCI controller is in the power-management D2 or D3 state, or if the OHCI configuration register
reset bit (SoftReset) is set, the OHCI controller DMA logic and link logic is reset.
Finally, if the OHCI configuration register PHY reset bit (ISBR) is set, the 1394 PHY logic is reset.
3.11.4 1394b OHCI PCI Bus Master
As a bus master, the 1394 OHCI function supports the memory commands specified in Table 3-8. The
commands include memory read, memory read line, memory read multiple, memory write, and memory
write and invalidate.
The read command usage for read transactions of greater than two data phases are determined by the
selection in bits 9:8 (MR_ENHANCE field) of the PCI miscellaneous configuration register at offset F0h
(see Section 7.21). For read transactions of one or two data phases, a memory read command is used.
The write command usage is determined by the MWI_ENB bit 4 of the command configuration register at
offset 04h (see Section 4.3). If bit 4 is asserted and a memory write starts on a cache boundary with a
length greater than one cache line, memory write and invalidate commands are used. Otherwise, memory
write commands are used.
46 Feature/Protocol Descriptions Copyright © 2008–2013, Texas Instruments Incorporated
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