Datasheet

XIO2213B
www.ti.com SCPS210F –OCTOBER 2008–REVISED MAY 2013
The link power management (LPM) state machine manages active-state power by monitoring the PCIe
transaction activity. If no transactions are pending and the transmitter has been idle for at least the
minimum time required by the PCI Express Specification, the LPM state machine transitions the link to
either the L0s or L1 state. By reading the bridges L0s and L1 exit latency in the link capabilities register,
the system software may make an informed decision relating to system performance versus power
savings. The ASLPMC field in the link control register provides an L0s-only option, L1-only option, or both
L0s and L1 options.
Finally, the bridge generates the PM_Active_State_Nak Message if a PM_Active_State_Request_L1
DLLP is received on the PCIe interface and the link cannot be transitioned to L1.
Copyright © 2008–2013, Texas Instruments Incorporated Feature/Protocol Descriptions 45
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