Datasheet

XIO2213B

SCPS210F –OCTOBER 2008–REVISED MAY 2013

www.ti.com

3.8 General-Purpose I/O (GPIO) Interface

Up to eight GPIO terminals are provided for system customization. These GPIO terminals are 3.3-V

tolerant.

The exact number of GPIO terminals varies based on implementing the clock-run, power-override, and

serial EEPROM interface features. These features share four of the eight GPIO terminals. When any of

the three shared functions are enabled, the associated GPIO terminal is disabled.

All eight GPIO terminals are individually configurable as either inputs or outputs by writing the

corresponding bit in the GPIO control register at offset B4h. A GPIO data register at offset B6h exists to

either read the logic state of each GPIO input or to set the logic state of each GPIO output. The power-up

default state for the GPIO control register is input mode.

3.9 Set Slot Power Limit Functionality

The PCI Express Specification provides a method for devices to limit internal functionality and save power

based on the value programmed into the captured slot power limit scale (CSPLS) and capture slot power

limit value (CSPLV) fields of the PCIe device capabilities register at offset 94h (see Section 4.50, Device

Capabilities Register, for details). The bridge writes these fields when a set slot power limit message is

received on the PCIe interface.

After the deassertion of PERST, the XIO2213B compares the information within the CSPLS and CSPLV

fields of the device capabilities register to the minimum power scale (MIN_POWER_SCALE) and minimum

power value (MIN_POWER_VALUE) fields in the general control register at offset D4h (see Section 4.66,

General Control Register, for details). If the CSPLS and CSPLV fields are less than the

MIN_POWER_SCALE and MIN_POWER_VALUE fields, respectively, the bridge takes the appropriate

action that is defined below.

The power usage action is programmable within the bridge. The general control register includes a 3-bit

POWER_OVRD field. This field is programmable to the following two options:

• Ignore slot power limit fields.

• Respond with unsupported request to all transactions except type 0/1 configuration transactions, and

set slot power limit messages.

3.10 PCIe and PCI Bus Power Management

The bridge supports both software-directed power management and active-state power management

through standard PCI configuration space. Software-directed registers are located in the power

management capabilities structure located at offset 50h. Active-state power management control registers

are located in the PCIe capabilities structure located at offset 90h.

During software-directed power-management state changes, the bridge initiates link state transitions to L1

or L2/L3 after a configuration write transaction places the device in a low-power state. The power-

management state machine is also responsible for gating internal clocks based on the power state.

Table 3-6 identifies the relationship between the D-states and bridge clock operation.

Table 3-6. Clocking In Low Power States

CLOCK SOURCE D0/L0 D1/L1 D2/L1 D3/L2/L3

PCIe reference clock input (REFCLK) On On On On/Off

Internal PCI bus clock to bridge function On Off Off Off

Internal PCI bus clock to 1394b OHCI function On On On On/Off

Submit Documentation Feedback

Product Folder Links: XIO2213B