Datasheet

S
1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0
A A
Slave Address
Word Address
R/W
DataByte1 DataByte2 DataByte3
M
P
M
M
M=Master Acknowledgement
S/P =Start/StopCondition
A =Slave Acknowledgement
DataByte0
M
S
1 1
0 0 0 0 0
1
A
Restart
R/W
Slave Address
Start
S
b6
b4
b5
b3
b2 b1
b0 0
b7
b6
b5
b4
b3
b2 b1
b0
A A
Slave Address
Word Address
R/W
S/P =Start/StopCondition
A =Slave Acknowledgement
b7
b6
b4
b5
b3
b2 b1
b0
A P
DataByte
XIO2213B
SCPS210F OCTOBER 2008REVISED MAY 2013
www.ti.com
Figure 3-9. Serial-Bus Protocol Byte Write
Figure 3-10 shows a single-byte read. The bridge issues a start condition and sends the 7-bit slave device
address, and the R/W command bit is equal to 0b (write). The slave device acknowledges if it recognizes
the slave address. Next, the EEPROM word address is sent by the bridge, and another slave
acknowledgment is expected. Then, the bridge issues a restart condition followed by the 7-bit slave
address, and the R/W command bit is equal to 1b (read). Once again, the slave device responds with an
acknowledge. Next, the slave device sends the 8-bit data byte, MSB first. Since this is a 1-byte read, the
bridge responds with no acknowledge (logic high) indicating the last data byte. Finally, the bridge issues a
stop condition.
Figure 3-10. Serial-Bus Protocol Byte Read
Figure 3-11 shows the serial interface protocol during a multibyte serial EEPROM download. The serial-
bus protocol starts exactly the same as a 1-byte read. The only difference is that multiple data bytes are
transferred. The number of transferred data bytes is controlled by the bridge master. After each data byte,
the bridge master issues acknowledge (logic low) if more data bytes are requested. The transfer ends
after a bridge master no acknowledge (logic high) followed by a stop condition.
Figure 3-11. Serial-Bus Protocol Multibyte Read
40 Feature/Protocol Descriptions Copyright © 2008–2013, Texas Instruments Incorporated
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