Datasheet

SCL
SDA
VDD_33
A0
A1
A2
SCL
SDA
XIO2213B
Serial
EEPROM
XIO2213B
SCPS210F OCTOBER 2008REVISED MAY 2013
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3.5 Two-Wire Serial-Bus Interface
The bridge provides a two-wire serial-bus interface to load subsystem identification information and
specific register defaults from an external EEPROM. The serial-bus interface signals are SCL and SDA.
3.5.1 Serial-Bus Interface Implementation
To enable the serial-bus interface, a pullup resistor must be implemented on the SDA signal. At the rising
edge of PERST or GRST, whichever occurs later in time, the SDA terminal is checked for a pullup
resistor. If one is detected, bit 3 (SBDETECT) in the serial-bus control and status register (see
Section 4.59) is set. Software may disable the serial-bus interface at any time by writing a 0b to the
SBDETECT bit. If no external EEPROM is required, the serial-bus interface is permanently disabled by
attaching a pulldown resistor to the SDA signal.
The bridge implements a two-terminal serial interface with one clock signal (SCL) and one data signal
(SDA). The SCL signal is a unidirectional output from the bridge and the SDA signal is bidirectional. Both
are open-drain signals and require pullup resistors. The bridge is a bus master device and drives SCL at
approximately 60 kHz during data transfers and places SCL in a high-impedance state (0 frequency)
during bus idle states. The serial EEPROM is a bus slave device and must acknowledge a slave address
equal to A0h. Figure 3-6 shows an example application implementing the two-wire serial bus.
Figure 3-6. Serial EEPROM Application
38 Feature/Protocol Descriptions Copyright © 2008–2013, Texas Instruments Incorporated
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