Datasheet

R
+0
+1 +2
+3
01
23
4567
0
12
3
4
5
6
77
6
5
4
3
2 1
0
7
6
5
4
3
2 1
0
Type
Fmt
0
1
1
0
1
0
0
R
TC
Reserved
ReservedID
0
0
0
Reserved
Tag
R
Length
Code
Attr
00
00
00
0
0
0
0
00
10
01
0
0
E
T
P
D
0
0
Byte0>
Byte4>
Byte8>
Byte12>
R
+0
+1 +2
+3
01
23
4567
0
12
3
4
5
6
77
6
5
4
3
2 1
0
7
6
5
4
3
2 1
0
Type
Fmt
0
1
1
0
1
0
0
R
TC
Reserved
ReservedID
0
0
0
Reserved
Tag
R
Length
Code
Attr
00
00
00
0
0
0
0
00
00
01
0
0
E
T
P
D
0
0
Byte0>
Byte4>
Byte8>
Byte12>
XIO2213B
www.ti.com SCPS210F –OCTOBER 2008–REVISED MAY 2013
3.4 PCI Interrupt Conversion to PCIe Messages
The bridge converts interrupts from the PCI bus sideband interrupt signals to PCIe interrupt messages.
Since the 1394a OHCI only generates INTA interrupts, only PCIe INTA messages are generated by the
bridge.
PCIe Assert_INTA messages are generated when the 1394a OHCI signals an INTA interrupt. The
requester ID portion of the Assert_INTA message uses the value stored in the primary bus number
register (see Section 4.12) as the bus number, 0 as the device number, and 0 as the function number.
The tag field for each Assert_INTA message is 00h.
PCIe Deassert_INTA messages are generated when the 1394a OHCI deasserts the INTA interrupt. The
requester ID portion of the Deassert_INTA message uses the value stored in the primary bus number
register as the bus number, 0 as the device number, and 0 as the function number. The Tag field for each
Deassert_INTA message is 00h.
Figure 3-4 and Figure 3-5 show the format for both the assert and deassert INTA messages.
Figure 3-4. PCIe Assert_INTA Message
Figure 3-5. PCIe Deassert_INTX Message
Copyright © 2008–2013, Texas Instruments Incorporated Feature/Protocol Descriptions 37
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