Datasheet

XIO2213B

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SCPS210F –OCTOBER 2008–REVISED MAY 2013

3.3 PCI Express (PCIe) Interface

3.3.1 External Reference Clock

The XIO2213B requires either a differential, 100-MHz common clock reference or a single-ended, 125-

MHz clock reference. The selected clock reference must meet all PCI Express Electrical Specification

requirements for frequency tolerance, spread-spectrum clocking, and signal electrical characteristics.

If the REFCLK_SEL input is connected to V

, a differential, 100-MHz common clock reference is

expected by the XIO2213B. If the REFCLK_SEL terminal is connected to V

DD_33

, a single-ended 125-MHz

clock reference is expected by the XIO2213B.

When the single-ended, 125-MHz clock reference option is enabled, the single-ended clock signal is

connected to the REFCLK+ terminal. The REFCLK terminal is connected to one side of an external

capacitor with the other side of the capacitor connected to V

When using a single-ended reference clock, care must be taken to ensure interoperability from a system

jitter standpoint. The PCI Express Base Specification does not ensure interoperability when using a

differential reference clock commonly used in PC applications along with a single-ended clock in a

noncommon clock architecture. System jitter budgets will have to be verified to ensure interoperability (see

the PCI Express Jitter and BER white paper from PCI-SIG).

3.3.2 Beacon and Wake

Since the 1394b OHCI function in the XIO2213B does not support PME from D3cold, it is not necessary

for the PCIe to PCI bridge portion of the design to support beacon generation or WAKE signaling. As a

result, the XIO2213B does not implement VAUX power support.

3.3.3 Initial Flow Control Credits

The bridge flow control credits are initialized using the rules defined in the PCI Express Base

Specification. Table 3-2 identifies the initial flow control credit advertisement for the bridge.

Table 3-2. Initial Flow Control Credit Advertisements

CREDIT TYPE INITIAL ADVERTISEMENT

Posted request headers (PH) 8

Posted request data (PD) 128

Nonposted header (NPH) 4

Nonposted data (NPD) 4

Completion header (CPLH) 0 (infinite)

Completion data (CPLD) 0 (infinite)

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