Datasheet

XIO2213B
SCPS210F –OCTOBER 2008–REVISED MAY 2013 www.ti.com
Table 2-9. 1394 Terminals (continued)
BALL NO.
I/O
SIGNAL DESCRIPTION
ZAY ZAJ
TYPE
PACKAGE PACKAGE
PINT_P D03 E03 O PHY-section interrupt. PINT_P is a serial input to the LLC section from the PHY
section that is used to transfer status, register, interrupt, and other information to the
link. Information encoded on PINT_P is synchronous to PCLK_P. This terminal must
be connected to the PINT_L input of the LLC section.
LKON/DS2_P D01 D02 I/O Link-on notification. If port is to operate in DS mode or is unused then it is necessary
to pull the terminal high through a 470-Ω or smaller resistor. This terminal must also
be connected to the LINKON_L input terminal of the LLC section via a 1-kΩ series
resistor. A bus holder is built into this terminal. If the port is to operate in bilingual
mode then the terminal should be tied low via a 1-kΩ resistor and directly connected
to the link's LINKON_L pin with no series termination. After hardware reset, this
terminal is the link-on output, which notifies the LLC section or other power-up logic
to power up and become active. The link-on output is a square-wave signal with a
period of approximately 163 ns (eight PCLK cycles) when active. The link-on output
is otherwise driven low, except during hardware reset when it is high impedance. The
link-on output is activated if the LLC section is inactive (the LPS input inactive or the
LCtrl bit cleared) and when any of the following occurs:
a) The XIO2213B receives a link-on PHY packet addressed to this node.
b) The PEI (port-event interrupt) register bit is 1.
c) Any of the configuration-timeout interrupt (CTOI), cable-power-status interrupt
(CPSI), or state-time-out interrupt (STOI) register bits are 1, and the resuming-port
interrupt enable (RPIE) register bit also is 1.
d) The PHY is power cycled and the power class is 0 through 4.
Once activated, the link-on output is active until the LLC section becomes active
(both the LPS_L input active and the LCtrl bit set). The PHY section also deasserts
the link-on output when a bus reset occurs unless the link-on output is otherwise
active because one of the interrupt bits is set (that is, the link-on output is active due
solely to the reception of a link-on PHY packet). In the case of power cycling, the
LKON signal must stop after 167 ms if the previous conditions have not been met.
Note: If an interrupt condition exists that otherwise causes the link-on output to be
activated if the LLC section were inactive, the link-on output is activated when the
LLC section subsequently becomes inactive.
LINKON_L E01 C02 I/O Link-on notification. LINKON_L is an input to the LLC section from the PHY section
that is used to provide notification that a link-on packet has been received or an
event, such as a port connection, has occurred. This I/O only has meaning when
LPS is disabled. This includes the D0 (uninitialized), D2, and D3 power states. If
LINKON_L becomes active in the D0 (uninitialized), D2, or D3 power state, the
XIO2213B device sets bit 15 (PME_STS) in the power-management control and
status register in the PCI configuration space at offset 48h. This terminal must be
connected to the LKON output terminal of the PHY section.
LREQ_L F02 D01 O LLC-section request. The LLC section uses this output to initiate a service request to
the PHY section.This terminal must be connected to the LREQ_P input of the PHY
section.
LREQ_P E02 E01 I LLC-section request. LREQ_P is a serial input from the LLC section to the PHY
section used to request packet transmissions, read and write PHY section registers,
and to indicate the occurrence of certain link events that are relevant to the PHY
section. Information encoded on LREQ_P is synchronous to LCLK_P.This terminal
must be connected to the LREQ_L output of the LLC section.
PHY_RESET B04 A06 I Reset for the 1394 PHY logic
CTL1 J01 G01 I/O Control. CTL[1:0] are bidirectional control bus signals that are used to indicate the
CTL0 H01 F01 phase of operation of the PHY link interface. Upon a reset of the interface, this bus is
driven by the PHY. When driven by the PHY, information on CTL[1:0] is synchronous
to PCLK. When driven by the link, information on CTL[1:0] is synchronous to LCLK.
If not implemented, these terminals should be left unconnected.
D0 J02 H01 I/O Data. D[7:0] comprise a bidirectional data bus that is used to carry 1394 packet data,
D1 K02 H02 packet speed, and grant type information between the PHY and the link. Upon a
D2 K01 J02 reset of the interface, this bus is driven by the PHY. When driven by the PHY,
D3 L01 J01 information on D[7:0] is synchronous to PCLK. When driven by the link, information
D4 L02 K02 on D[7:0] is synchronous to LCLK. If not implemented, these terminals should be left
D5 L03 K01 unconnected.
D6 M02 L01
D7 M03 M01
28 Overview Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: XIO2213B