Datasheet

XIO2213B
www.ti.com SCPS210F –OCTOBER 2008–REVISED MAY 2013
Table 2-9. 1394 Terminals
BALL NO.
I/O
SIGNAL DESCRIPTION
ZAY ZAJ
TYPE
PACKAGE PACKAGE
CNA A02 A02 I/O Cable not active. This terminal is asserted high when there are no ports receiving
incoming bias voltage. If it is not used, this terminal should be left unconnected.
CPS P12 N09 I Cable power status. This terminal is normally connected to cable power through a
400-kΩ resistor. This circuit drives an internal comparator that detects the presence
of cable power. If CPS is not used to detect cable power, this terminal must be
connected to V
SSA
.
DS0 N09 N08 I Data-strobe-only mode for port 0. IEEE Std 1394a-2000-only port-0-enable
programming terminal. On hardware reset, this terminal allows the user to select
whether port 0 acts like an IEEE Std 1394b-2002 bilingual port (terminal at logic 0) or
as an IEEE Std 1394a-2000-only port (terminal at logic 1). Programming is
accomplished by tying the terminal low through a 1-kΩ or smaller resistor (to enable
IEEE Std 1394b-2002 bilingual mode) or high through a 10-kΩ or smaller resistor (to
enable IEEE Std 1394a-2000-only mode).
DS1 P09 M07 I Data-strobe-only mode for port 1. IEEE Std 1394a-2000-only port-1-enable
programming terminal. On hardware reset, this terminal allows the user to select
whether port 1 acts like an IEEE Std 1394b-2002 bilingual port (terminal at logic 0) or
as an IEEE Std 1394a-2000-only port (terminal at logic 1). Programming is
accomplished by tying the terminal low through a 1-kΩ or smaller resistor (to enable
IEEE Std 1394b-2002 bilingual mode) or high through a 10-kΩ or smaller resistor (to
enable IEEE Std 1394a-2000-only mode).
PC0 E09 C11 I Power-class programming. On hardware reset, these inputs set the default value of
PC1 E08 A09 the power class indicated during self-ID. Programming is done by tying the terminals
PC2 A11 B08 high through a 1-kΩ or smaller resistor or by tying directly to ground through a 1-kΩ
or smaller resistor. Bus holders are built into these terminals.
R0 N01 N03 I/O Current-setting resistor. These terminals are connected to an external resistance to
R1 M01 N02 set the internal operating currents and cable driver output currents. A resistance of
6.34 kΩ ± 1% is required to meet the IEEE Std 1394-1995 output voltage limits.
TPA0P K14 J13 I/O Port 0 twisted-pair cable A differential. Board trace lengths from each pair of positive
TPA0N L14 K13 and negative differential signal pins must be matched and as short as possible to the
TPB0P M14 L13 external load resistors and to the cable connector. For an unused port, TPA+ and
TPB0N N14 M13 TPA– can be left open.
TPA1P F14 E13 I/O Port 1 twisted-pair cable A differential. Board trace lengths from each pair of positive
TPA1N G14 F13 and negative differential signal pins must be matched and as short as possible to the
TPB1P H14 G13 external load resistors and to the cable connector. For an unused port, TPA+ and
TPB1N J14 H13 TPA– can be left open.
TPA2P B14 A13 I/O Port 2 twisted-pair cable A differential. Board trace lengths from each pair of positive
TPA2N C14 B13 and negative differential signal pins must be matched and as short as possible to the
TPB2P D14 C13 external load resistors and to the cable connector. For an unused port, TPA+ and
TPB2N E14 D13 TPA– can be left open.
TPBIAS0 K13 J12 O Twisted-pair bias. These terminals provide the 1.86-V nominal bias voltage needed
TPBIAS1 G13 E12 for proper operation of the twisted-pair cable drivers and receivers, and for signaling
TPBIAS2 E13 A12 to the remote nodes that there is an active cable connection in IEEE Std 1394a-2000
mode. Each of these terminals, except for an unused port, must be decoupled with a
1-μF capacitor to ground. For the unused port, this terminal can be left unconnected.
PCLK_L G01 F03 I PHY-section clock. This terminal must be connected to the PCLK_P output of the
PHY section.
PCLK_P F01 F02 O PHY-section clock. This terminal must be connected to the PCLK_L input of the LLC
section.
LCLK_L G02 G03 O LLC-section clock. This terminal must be connected to the LCLK_P input terminal of
the PHY section.
LCLK_P H02 G02 I LLC-section clock. This terminal must be connected to the LCLK_L output terminal of
the LLC section.
LPS_L C01 C03 O LLC-section power status. This terminal must be connected to the LPS_P input
terminal of the PHY section.
LPS_P C02 D03 I Link power status. This terminal must be connected to the LPS_L ouput terminal of
the LLC section.
PINT_L D02 E02 I PHY-section interrupt. The PHY section uses this signal to transfer status and
interrupt information serially to the LLC section. This terminal must be connected to
the PINT_P output of the PHY section.
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