Datasheet

XIO2213B
SCPS210F –OCTOBER 2008–REVISED MAY 2013 www.ti.com
Table 2-6. Ground Terminals
BALL NO.
I/O
SIGNAL DESCRIPTION
ZAY ZAJ
TYPE
PACKAGE PACKAGE
V
SS
A07 A14 E07 E08 GND Digital ground for link
V
SSA
B06 C10 F05 D04 D07 E09 GND Analog ground for link
V
SSA_PCIE
C04 C05 C06 C07 C06 D05 D06 E06 GND Analog ground for PCIe function
PLLGND N05 N04 GND PLL circuit ground. This terminal must be tied to the low-
impedance circuit-board ground plane.
GND E06 E07 F06 F07 F08 E05 F04 F05 F06 F07 GND Ground. These terminals must be tied together to the low-
F09 G05 G06 G07 G08 F08 F09 G04 G05 G06 impedance circuit-board ground plane.
G09 H05 H06 H07 H08 G07 G08 G09 G10 H04
H09 J05 J06 J07 J08 H05 H06 H07 H08 J04
K05 K06 K07 K08 J05 J06 J07 J08 K07
L07
Table 2-7. PCIe Terminals
BALL NO.
I/O EXTERNAL
SIGNAL DESCRIPTION
ZAY ZAJ
TYPE PARTS
PACKAGE PACKAGE
PERST B13 B12 I PCI Express reset. PERST identifies when the system power is stable
and generates an internal power-on reset.
Note: The PERST input buffer has hysteresis.
REF0_PCIE A13 A11 I/O External External reference resistor + and terminals for setting TX driver current.
REF1_PCIE A12 A10 resistor An external resistor is connected between terminals REF0_PCIE and
REF1_PCIE.
RXP A04 A05 DI High-speed receive pair. RXP and RXN comprise the differential
RXN A03 A04 receive pair for the single PCIe lane supported.
TXP A09 A08 DO Series High-speed transmit pair. TXP and TXN comprise the differential
TXN A08 A07 capacitors transmit pair for the single PCIe lane supported.
Table 2-8. Clock Terminals
BALL NO.
I/O EXTERNAL
SIGNAL DESCRIPTION
ZAY ZAJ
TYPE PARTS
PACKAGE PACKAGE
REFCLK_SEL H13 G11 I Pullup or Reference clock select. This terminal selects the reference clock input.
pulldown
0 = 100-MHz differential common reference clock used
resistor
1 = 125-MHz single-ended reference clock used
REFCLK+ A01 B01 DI Reference clock positive. REFCLK+ and REFCLK– comprise the
differential input pair for the 100-MHz system reference clock. For a
single-ended, 125-MHz system reference clock, use the REFCLK+
input.
REFCLK– B01 C01 DI Capacitor to Reference clock negative. REFCLK+ and REFCLK– comprise the
V
SS
for differential input pair for the 100-MHz system reference clock. For a
single- single-ended, 125-MHz system reference clock, attach a capacitor from
ended REFCLK– to V
SS
.
mode
CLKREQ J12 H12 O Clock request. This terminal is used to support the clock request
protocol.
XI P04 N05 I Oscillator input. This terminal connects to a 98.304-MHz low-jitter
external oscillator. XI is a 1.8-V CMOS input. Oscillator jitter must be 5-
ps RMS or better. If only 3.3-V oscillators can be acquired, great care
must be taken to not introduce significant jitter by the means used to
level shift from 3.3 V to 1.8 V. If a resistor divider is used, a high-current
oscillator and low-value resistors must be used to minimize RC time
constants.
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