Datasheet

XIO2213B
SCPS210F –OCTOBER 2008–REVISED MAY 2013 www.ti.com
11.5 PCIe Differential Reference Clock Input Ranges
(1)
REFCLK+ and REFCLK–
PARAMETER MIN NOM MAX UNIT COMMENTS
The input frequency is 100 MHz + 300 ppm and
f
IN-DIFF
Differential input frequency 100 MHz
2800 ppm including SSC-dictated variations.
The input frequency is 125 MHz + 300 ppm and
f
IN-SE
Single-ended input frequency 125 MHz
300 ppm.
Differential input peak-to-peak
V
RX-DIFFp-p
0.175 1.200 V V
RX-DIFFp-p
= 2*|V
REFCLK+
V
REFCLK–
|R
voltage
Single-ended, reference clock mode high-level
V
IH-SE
REFCLK+ only 0.7 V
DD_33
V
DD_33
V
input voltage
Single-ended, reference clock mode low-level
V
IL-SE
REFCLK+ only 0 0.3 V
DD_33
V
input voltage
V
RX-CM-ACp
= RMS(|V
REFCLK+
+ V
REFCLK–
|/2 V
RX-CM-
AC peak common-mode input
V
RX-CM-ACp
140 mV
DC
) V
RX-CM-DC
= DC
(avg)
of
voltage
|V
REFCLK+
+ V
REFCLK–
|/2
Differential and single-ended waveform input duty
Duty cycle 40% 60%
cycle
Z
RX-DIFF-DC
DC differential input impedance 20 k REFCLK– dc differential mode impedance
Z
RX-DC
DC input impedance 20 k REFCLK+ dc single-ended mode impedance
(1) The XIO2213B is compliant with the defined system jitter models for a PCIe reference clock and associated TX/RX link. These system
jitter models are described in the PCI Express Jitter Modeling, Revision 1.0 RD document. Any usage of the XIO2213B in a system
configuration that does not conform to the defined system jitter models requires the system designer to validate the system jitter
budgets.
11.6 Electrical Characteristics Over Recommended Operating Conditions (3.3-V I/O)
PERST, WAKE, REFCLK_SEL, GRST, GPIO[7:0], CNA, PC[2:0], and all RSVD terminals
PARAMETER OPERATION TEST CONDITIONS MIN MAX UNIT
V
IH
High-level input voltage
(1)
V
DD_33
0.7 V
DD_33
V
DD_33
V
V
IL
Low-level input voltage
(1)
V
DD_33
0 0.3 V
DD_33
V
V
I
Input voltage 0 V
DD_33
V
V
O
Output voltage
(2)
0 V
DD_33
V
t
T
Input transition time (t
rise
and t
fall
) 0 25 ns
V
hys
Input hysteresis
(3)
0.3 V
DD_33
V
V
OH
High-level output voltage V
DD_33
I
OH
= 4 mA 0.8 V
DD_33
V
V
OL
Low-level output voltage V
DD_33
I
OL
= 4 mA 0.22 V
DD_33
V
I
OZ
High-impedance, output current
(2)
V
DD_33
V
I
= 0 to V
DD_33
20 μA
High-impedance, output current with internal
I
OZP
V
DD_33
V
I
= 0 to V
DD_33
100 μA
pullup or pulldown resistor
(4)
I
I
Input current
(5)
V
DD_33
V
I
= 0 to V
DD_33
1 μA
(1) Applies to external inputs and bidirectional buffers
(2) Applies to external outputs and bidirectional buffers
(3) Applies to PERST and GRST
(4) Applies to GRST (pullup resistor) and most GPIOs (pullup resistor)
(5) Applies to external input buffers
194 Electrical Characteristics Copyright © 2008–2013, Texas Instruments Incorporated
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