Datasheet

XIO2213B
www.ti.com SCPS210F –OCTOBER 2008–REVISED MAY 2013
10.2.4 Bus Reset
It is recommended that whenever the user has a choice, the user should initiate a bus reset by writing to
the initiate short bus reset (ISBR) bit (bit 1, PHY register 0101b). Care must be taken not to change the
value of any of the other writeable bits in this register when the ISBR bit is written to.
In the XIO2213B, the initiate bus reset (IBR) bit can be set to 1 in order to initiate a bus reset and
initialization sequence; however, it is recommended to use the ISBR bit instead. The IBR bit is located in
PHY register 1 along with the root holdoff bit (RHB) and gap count. As required by the IEEE Std 1394b-
2002 Supplement, this configuration maintains compatibility with older TI PHY designs that were based on
either the suggested register set defined in Annex J of IEEE Std 1394-1995 or the IEEE Std 1394a-2000
Supplement. Therefore, whenever the IBR bit is written, the RHB and gap count are also necessarily
written.
It is recommended that the RHB and gap count only be updated by PHY configuration packets. The
XIO2213B is IEEE Std 1394a-2000 and IEEE Std 1394b-2002 compliant and, therefore, both the reception
and transmission of PHY configuration packets cause the RHB and gap count to be loaded, unlike older
IEEE Std 1394-1995-compliant PHYs that decode only received PHY configuration packets.
The gap count is set to the maximum value of 63 after two consecutive bus resets without an intervening
write to the gap count, either by a write to PHY register 1 or by a PHY configuration packet. This
mechanism allows a PHY configuration packet to be transmitted and then a bus reset initiated to verify
that all nodes on the bus have updated their RHBs and gap counts, without having the gap count set back
to 63 by the bus reset. The subsequent connection of a new node to the bus, which initiates a bus reset,
then causes the gap count of each node to be set to 63. Note, however, that if a subsequent bus reset is
instead initiated by a write to register 1 to set the IBR bit, all other nodes on the bus have their gap counts
set to 63, while this nodes gap count remains set to the value just loaded by the write to PHY register 1.
Therefore, in order to maintain consistent gap counts throughout the bus, the following rules apply to the
use of the IBR bit, RHB, and gap count in PHY register 1:
• Following the transmission of a PHY configuration packet, a bus reset must be initiated in order to
verify that all nodes have correctly updated their RHBs and gap counts, and to ensure that a
subsequent new connection to the bus causes the gap count to be set to 63 on all nodes in the bus. If
this bus reset is initiated by setting the IBR bit to 1, the RHB and gap count register must also be
loaded with the correct values consistent with the just-transmitted PHY configuration packet. In the
XIO2213B, the RHB and gap count have been updated to their correct values on the transmission of
the PHY configuration packet, so these values can first be read from register 1 and then rewritten.
• Other than to initiate the bus reset that must follow the transmission of a PHY configuration packet,
when the IBR bit is set to 1 in order to initiate a bus reset, the gap count must also be set to 63 to be
consistent with other nodes on the bus, and the RHB must be maintained with its current value.
• The PHY register 1 must not be written to except to set the IBR bit. The RHB and gap count must not
be written without also setting the IBR bit to 1.
• To avoid these problems, all bus resets initiated by software must be initiated by writing the ISBR bit
(bit 1 PHY register 0101b). Care must be taken to not change the value of any of the other writeable
bits in this register when the ISBR bit is written to. Also, the only means to change the gap count of
any node must be by means of the PHY configuration packet, which changes all nodes to the same
gap count.
Copyright © 2008–2013, Texas Instruments Incorporated Physical Layer (PHY) Section 189
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