Datasheet

XIO2213B
SCPS210F –OCTOBER 2008–REVISED MAY 2013 www.ti.com
When the XIO2213B PHY section is used without one or more of the ports brought out to a connector,
the twisted-pair terminals of the unused ports must be terminated for reliable operation. For each
unused port, the port must be forced to the IEEE Std 1394a-2000-only mode (data-strobe-only mode)
by pulling DSn to VCC through a 1KΩ resistor, after which the TPB+ and TPB– terminals can be tied
together and then pulled to ground; or TPB+ and TPB– can be connected to the suggested normal
termination network. TPA+ and TPA– of an unused port can be left unconnected. The TPBIAS terminal
can be connected through a 1-μF capacitor to ground or left unconnected.
The TESTM, SE, and SM terminals are used to set up various manufacturing test conditions. For
normal operation, TESTM must be connected to VDD through a 1-kΩ resistor. The SE and SM
terminals must be tied to ground through a 1-kΩ resistor.
The LPS_P (link power status) terminal of the PHY section works with the LKON terminal to manage
the power usage in the node. The LPS_L signal from the LLC section is used in conjunction with the
LCtrl bit (see Table 10-1 and Table 10-2 ) to indicate the active/power status of the LLC section. The
LPS_P signal also resets, disables, and initializes the PHY-section/LLC-section interface (the state of
the PHY-section/LLC-section interface is controlled solely by the LPS_P input, regardless of the state
of the LCtrl bit). The LPS_P terminal of the PHY section must be connected to the LPS_L terminal of
the LLC section during normal operation.
The LPS_P input is considered inactive if it remains low for more than the PHY_RESET time (see the
LPS terminal definition) and is considered active otherwise. When the PHY section detects that the
LPS_P input is inactive, the PHY-section/LLC-section interface is placed into a low-power reset state in
which the CTL and D outputs are held in the logic 0 state and the LREQ input is ignored; however, the
PCLK output remains active. If the LPS input remains low for more than the LPS_DISABLE time (see
the LPS terminal definition), the PHY-section/LLC-section interface is put into a low-power disabled
state in which the PCLK_P output is also held inactive. The XIO2213B continues the necessary PHY
repeater functions required for normal network operation, regardless of the state of the PHY-
section/LLC-section interface. When the interface is in the reset or disabled state and the LPS input is
again observed active, the PHY section initializes the interface and returns to normal operation. The
PHY-section/LLC-section interface is also held in the disabled state during hardware reset. When the
LPS_P terminal is returned to an active state after being sensed as having entered the LPS_DISABLE
time, the XIO2213B issues a bus reset. This broadcasts the node self-ID packet, which contains the
updated L bit state (the PHY section and LLC section now being accessible).
The PHY section uses the LKON terminal to notify the LLC section to power up and become active.
When activated, the output LKON signal is a square wave. The PHY section activates the LKON
output when the LLC section is inactive and a wake-up event occurs. The LLC section is considered
inactive when either the LPS_P input is inactive, as previously described, or the LCtrl bit is cleared to
0. A wake-up event occurs when a link-on PHY packet addressed to this node is received, or
conditionally when a PHY interrupt occurs. The PHY section deasserts the LKON output when the LLC
section becomes active (both LPS_P sensed as active and the LCtrl bit set to 1). The PHY section also
deasserts the LKON output when a bus reset occurs, unless a PHY interrupt condition exists, which
would otherwise cause LKON to be active. If the XIO2213B is power cycled and the power class is 0
through 4, the PHY section asserts LKON for approximately 167 ms or until both the LPS_P is active
and the LCtrl bit is 1.
10.1 PHY Section Register Configuration
There are 16 accessible PHY section registers in the XIO2213B. The configuration of the registers at
addresses 0h through 7h (the base registers) is fixed, while the configuration of the registers at addresses
8h through Fh (the paged registers) is dependent on which of eight pages, numbered 0h through 7h, is
currently selected. The selected page is set in base register 7h. Note that while this register set is
compatible with IEEE Std 1394a-2000 register sets, some fields have been redefined and this register set
contains additional fields.
Table 10-1 shows the configuration of the base registers, and Table 10-2 gives the corresponding field
descriptions. The base register field definitions are unaffected by the selected page number.
180 Physical Layer (PHY) Section Copyright © 2008–2013, Texas Instruments Incorporated
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