Datasheet

XIO2213B

SCPS210F –OCTOBER 2008–REVISED MAY 2013

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9.5 Timestamp Offset Registers

The value of these registers is added as an offset to the cycle timer value when using the MPEG, DV, and

CIP enhancements. A timestamp offset register is implemented per isochronous transmit context. The n

value following the offset indicates the context number (n = 0, 1, 2, 3, ..., 7). These registers are

programmed by software as appropriate. See Table 9-4 for a complete description of the register contents.

TI extension register offset: A90h + (4*n)

Default value: 0000 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 9-4. Timestamp Offset Registers Description

BIT FIELD NAME TYPE DESCRIPTION

31 DisableInitialOffset RW Bit 31 disables the use of the initial timestamp offset when the MPEG2 enhancements are

enabled. A value of 0b indicates the use of the initial offset, a value of 1b indicates that the

initial offset must not be applied to the calculated timestamp. This bit has no meaning for the

DV timestamp enhancements. The default value for this bit is 0b.

3-=25 RSVD R Reserved. Bits 30-25 return 000 0000b when read.

24-12 CycleCount RW This field adds an offset to the cycle count field in the timestamp when the DV or MPEG2

enhancements are enabled. The cycle count field is incremented modulo 8000; therefore,

values in this field must be limited between 0 and 7999. The default value for this field is all 0s.

11-0 CycleOffset RW This field adds an offset to the cycle offset field in the timestamp when the DV or MPEG2

enhancements are enabled. The cycle offset field is incremented modulo 3072; therefore,

values in this field must be limited between 0 and 3071. The default value for this field is all 0s.

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