Datasheet

XIO2213B
www.ti.com SCPS210F –OCTOBER 2008–REVISED MAY 2013
Table 8-34. Isochronous Receive Context Control Register Description
BIT FIELD NAME TYPE DESCRIPTION
31 bufferFill RSC Buffer fill. When bit 31 is set to 1b, received packets are placed back to back to completely fill
each receive buffer. When this bit is cleared, each received packet is placed in a single buffer.
If bit 28 (multiChanMode) is set to 1b, this bit must also be set to 1b. The value of this bit must
not be changed while bit 10 (active) or bit 15 (run) is set to 1b.
30 isochHeader RSC Isochronous header. When bit 30 is set to 1b, received isochronous packets include the
complete 4-byte isochronous packet header seen by the link layer. The end of the packet is
marked with a xferStatus in the first doublet, and a 16-bit timestamp indicating the time of the
most recently received (or sent) cycleStart packet.
When this bit is cleared, the packet header is stripped from received isochronous packets. The
packet header, if received, immediately precedes the packet payload. The value of this bit must
not be changed while bit 10 (active) or bit 15 (run) is set to 1b.
29 cycleMatchEnable RSCU Cycle match enable. When bit 29 is set to 1b and the 13-bit cycleMatch field (bits 24-12) in the
isochronous receive context match register (See Section 8.46) matches the 13-bit cycleCount
field in the cycleStart packet, the context begins running. The effects of this bit, however, are
impacted by the values of other bits in this register. Once the context has become active,
hardware clears this bit. The value of this bit must not be changed while bit 10 (active) or bit 15
(run) is set to 1b.
28 multiChanMode RSC Multichannel mode. When bit 28 is set to 1b, the corresponding isochronous receive DMA
context receives packets for all isochronous channels enabled in the isochronous receive
channel mask high register at OHCI offset 70h/74h (see Section 8.19) and isochronous receive
channel mask low register at OHCI offset 78h/7Ch (see Section 8.20). The isochronous channel
number specified in the isochronous receive context match register (see Section 8.46) is
ignored.
When this bit is cleared, the isochronous receive DMA context receives packets for the single
channel specified in the isochronous receive context match register (see Section 8.46). Only
one isochronous receive DMA context may use the isochronous receive channel mask registers
(see Section 8.19, and Section 8.20). If more than one isochronous receive context control
register has this bit set, the results are undefined. The value of this bit must not be changed
while bit 10 (active) or bit 15 (run) is set to 1b.
27 dualBufferMode RSC Dual-buffer mode. When bit 27 is set to 1b, receive packets are separated into first and second
payload and streamed independently to the firstBuffer series and secondBuffer series as
described in Section 10.2.3 in the 1394 Open Host Controller Interface Specification. Also,
when bit 27 is set to 1b, both bits 28 (multiChanMode) and 31 (bufferFill) are cleared to 00b.
The value of this bit does not change when either bit 10 (active) or bit 15 (run) is set to 1b.
26-16 RSVD R Reserved. Bits 26-16 return 000 0000 0000b when read.
15 run RSCU Run. Bit 15 is set to 1b by software to enable descriptor processing for the context and cleared
by software to stop descriptor processing. The controller changes this bit only on a system
(hardware) or software reset.
14-13 RSVD R Reserved. Bits 14 and 13 return 00b when read.
12 wake RSU Wake. Software sets bit 12 to 1b to cause the controller to continue or resume descriptor
processing. The controller clears this bit on every descriptor fetch.
11 dead RU Dead. The controller sets bit 11 to 1b when it encounters a fatal error, and clears the bit when
software clears bit 15 (run).
10 active RU Active. The controller sets bit 10 to 1b when it is processing descriptors.
9 betaFrame RU Beta frame. Set to 1 when the PHY indicates that the received packet is sent in beta format. A
response to a request sent using beta format also uses beta format.
9-8 RSVD R Reserved. Bit 8 returns 0b when read.
7-8 spd RU Speed. This field indicates the speed at which the packet was received.
000 = 100M bit/s
001 = 200M bit/s
010 = 400M bit/s
011 = 800M bit/s0
All other values are reserved.
4-0 event code RU For bufferFill mode, possible values are ack_complete, evt_descriptor_read, evt_data_write,
and evt_unknown. Packets with data errors (either dataLength mismatches or dataCRC errors)
and packets for which a FIFO overrun occurred are backed out. For packet-per-buffer mode,
possible values are ack_complete, ack_data_error, evt_long_packet, evt_overrun,
evt_descriptor_read, evt_data_write, and evt_unknown.
Copyright © 2008–2013, Texas Instruments Incorporated 1394 OHCI Memory-Mapped Register Space 171
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