Datasheet

XIO2213B

SCPS210F –OCTOBER 2008–REVISED MAY 2013

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8.43 Isochronous Transmit Context Command Pointer Register

The isochronous transmit context command pointer register contains a pointer to the address of the first

descriptor block that the controller accesses when software enables an isochronous transmit context by

setting bit 15 (run) in the isochronous transmit context control register (see Section 8.42) to 1b. The

isochronous transmit DMA context command pointer can be read when a context is active. The n value in

the following register addresses indicates the context number (n = 0, 1, 2, 3, ..., 7).

OHCI register offset: 20Ch + (16 * n)

Default value: XXXX XXXXh

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE X X X X X X X X X X X X X X X X

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE X X X X X X X X X X X X X X X X

8.44 Isochronous Receive Context Control Register

The isochronous receive context control set/clear register controls options, state, and status for the

isochronous receive DMA contexts. The n value in the following register addresses indicates the context

number (n = 0, 1, 2, 3). See Table 8-34 for a complete description of the register contents.

OHCI register offset: 400h + (32 * n) set register

404h + (32 * n) clear register

Read/Update, Read only

Default value: XX00 X0XXh

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE X X X X X 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 X 0 0 0 0 X X X X X X X X

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