Datasheet

XIO2213B
www.ti.com SCPS210F –OCTOBER 2008–REVISED MAY 2013
8.40 Asynchronous Context Control Register
The asynchronous context control set/clear register controls the state and indicates status of the DMA
context. See Table 8-31 for a complete description of the register contents.
OHCI register offset: 180h set register (ATRQ)
184h clear register (ATRQ)
1A0h set register [ATRS]
1A4h clear register [ATRS]
1C0h set register (ARRQ)
1C4h clear register (ARRQ)
1E0h set register (ARRS)
1E4h clear register (ARRS)
Register type: Read/Set/Clear/Update, Read/Set/Update, Read/Update, Read only
Default value: 0000 X0XXh
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 X 0 0 0 0 X X X X X X X X
Table 8-31. Asynchronous Context Control Register Description
BIT FIELD NAME TYPE DESCRIPTION
31-16 RSVD R Reserved. Bits 31-16 return 0000h when read.
15 run RSCU Run. Bit 15 is set to 1b by software to enable descriptor processing for the context and cleared
by software to stop descriptor processing. The controller changes this bit only on a system
(hardware) or software reset.
14-13 RSVD R Reserved. Bits 14 and 13 return 00b when read.
12 wake RSU Wake. Software sets bit 12 to 1b to cause the controller to continue or resume descriptor
processing. The controller clears this bit on every descriptor fetch.
11 dead RU Dead. The controller sets bit 11 to 1b when it encounters a fatal error, and clears the bit when
software clears bit 15 (run). Asynchronous contexts supporting out-of-order pipelining provide
unique ContextControl.dead functionality. See Section 7.7 in the 1394 Open Host Controller
Interface Specification, Release 1.1 for more information.
10 active RU Active. The controller sets bit 10 to 1b when it is processing descriptors.
9 betaFrame RU Beta frame. Set to 1 when the PHY indicates that the received packet is sent in beta format. A
response to a request sent using beta format also uses beta format.
8 RSVD R Reserved. Bit 8 returns 0b when read.
7-5 spd RU Speed. This field indicates the speed at which a packet was received or transmitted and only
contains meaningful information for receive contexts. This field is encoded as:
000 = 100M bit/s
001 = 200M bit/s
010 = 400M bit/s
011 = 800M bit/s0
All other values are reserved.
4-0 eventcode RU Event code. This field holds the acknowledge sent by the link core for this packet or an internally-
generated error code if the packet was not transferred successfully.
Copyright © 2008–2013, Texas Instruments Incorporated 1394 OHCI Memory-Mapped Register Space 167
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