Datasheet

XIO2213B
SCPS210F –OCTOBER 2008–REVISED MAY 2013 www.ti.com
8.38 Physical Request Filter Low Register
The physical request filter low set/clear register enables physical receive requests on a per-node basis,
and handles the lower node IDs. When a packet is destined for the physical request context and the node
ID has been compared against the asynchronous request filter registers, the node ID comparison is done
again with this register. If the bit corresponding to the node ID is not set to 1b in this register, the request
is handled by the asynchronous request context instead of the physical request context. See Table 8-30
for a complete description of the register contents.
OHCI register offset: 118h set register
11Ch clear register
Register type: Read/Set/Clear
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 8-30. Physical Request Filter Low Register Description
BIT FIELD NAME TYPE DESCRIPTION
31 physReqResource3 RSC If bit 31 is set to 1b for local bus node number 31, physical requests received by the controller
1 from that node are handled through the physical request context.
30 physReqResource3 RSC If bit 30 is set to 1b for local bus node number 30, physical requests received by the controller
0 from that node are handled through the physical request context.
29-2 physReqResourcen RSC Bits 29 through 2 (physReqResourcen, where n = 29, 28, 27, ..., 2) follow the same pattern as
bits 31 and 30.
1 physReqResource1 RSC If bit 1 is set to 1b for local bus node number 1, physical requests received by the controller from
that node are handled through the physical request context.
0 physReqResource0 RSC If bit 0 is set to 1b for local bus node number 0, physical requests received by the controller from
that node are handled through the physical request context.
8.39 Physical Upper Bound Register (Optional Register)
The physical upper bound register is an optional register and is not implemented. This register returns
0000 0000h when read.
OHCI register offset: 120h
Register type: Read only
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
166 1394 OHCI Memory-Mapped Register Space Copyright © 2008–2013, Texas Instruments Incorporated
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