Datasheet

XIO2213B
www.ti.com SCPS210F –OCTOBER 2008–REVISED MAY 2013
8.36 Asynchronous Request Filter Low Register
The asynchronous request filter low set/clear register enables asynchronous receive requests on a per-
node basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves
identically to the asynchronous request filter high register. See Table 8-28 for a complete description of
the register contents.
OHCI register offset: 108h set register
10Ch clear register
Register type: Read/Set/Clear
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 8-28. Asynchronous Request Filter Low Register Description
BIT FIELD NAME TYPE DESCRIPTION
31 asynReqResource31 RSC If bit 31 is set to 1b for local bus node number 31, asynchronous requests received by the
controller from that node are accepted.
30 asynReqResource30 RSC If bit 30 is set to 1b for local bus node number 30, asynchronous requests received by the
controller from that node are accepted.
29-2 asynReqResourcen RSC Bits 29 through 2 (asynReqResourcen, where n = 29, 28, 27, ..., 2) follow the same pattern
as bits 31 and 30.
1 asynReqResource1 RSC If bit 1 is set to 1b for local bus node number 1, asynchronous requests received by the
controller from that node are accepted.
0 asynReqResource0 RSC If bit 0 is set to 1b for local bus node number 0, asynchronous requests received by the
controller from that node are accepted.
8.37 Physical Request Filter High Register
The physical request filter high set/clear register enables physical receive requests on a per-node basis,
and handles the upper node IDs. When a packet is destined for the physical request context and the node
ID has been compared against the ARRQ registers, the comparison is done again with this register. If the
bit corresponding to the node ID is not set to 1b in this register, the request is handled by the ARRQ
context instead of the physical request context. The node ID comparison is done if the source node is on
the same bus as the controller. Nonlocal bus-sourced packets are not acknowledged unless bit 31 in this
register is set to 1b. See Table 8-29 for a complete description of the register contents.
OHCI register offset: 110h set register
114h clear register
Register type: Read/Set/Clear
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Copyright © 2008–2013, Texas Instruments Incorporated 1394 OHCI Memory-Mapped Register Space 163
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