Datasheet

XIO2213B
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SCPS210F OCTOBER 2008REVISED MAY 2013
8.28 Initial Channels Available High Register
The initial channels available high register value is loaded into the corresponding bus-management CSR
register on a system (hardware) or software reset. See Table 8-20 for a complete description of the
register contents.
OHCI register offset: B4h
Register type: Read/Write
Default value: FFFF FFFFh
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Table 8-20. Initial Channels Available High Register Description
BIT FIELD NAME TYPE Description
31-0 InitChanAvailHi RW This field is reset to FFFF_FFFFh on a system (hardware) or software reset, and is not affected by
a 1394 bus reset. The value of this field is loaded into the CHANNELS_AVAILABLE_HI CSR
register upon a GRST, PERST, PRST, or 1394 bus reset.
8.29 Initial Channels Available Low Register
The initial channels available low register value is loaded into the corresponding bus-management CSR
register on a system (hardware) or software reset. See Table 8-21 for complete description of the register
contents.
OHCI register offset: B8h
Register type: Read/Write
Default value: FFFF FFFFh
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Table 8-21. Initial Channels Available Low Register Description
BIT FIELD NAME TYPE DESCRIPTION
31-0 InitChanAvailLo RW This field is reset to FFFF_FFFFh on a system (hardware) or software reset, and is not affected by
a 1394 bus reset. The value of this field is loaded into the CHANNELS_AVAILABL_LO CSR register
upon a GRST, PRST, PRST, or 1394 bus reset.
Copyright © 2008–2013, Texas Instruments Incorporated 1394 OHCI Memory-Mapped Register Space 155
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