Datasheet

XIO2213B
SCPS210F –OCTOBER 2008–REVISED MAY 2013 www.ti.com
8.26 Isochronous Receive Interrupt Mask Register
The isochronous receive interrupt mask set/clear register enables the isochRx interrupt source on a per-
channel basis. Reads from either the set register or the clear register always return the contents of the
isochronous receive interrupt mask register. In all cases, the enables for each interrupt event align with
the isochronous receive interrupt event register bits detailed in Table 8-18.
OHCI register offset: A8h set register
ACh clear register
Register type: Read/Set/Clear, Read only
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
8.27 Initial Bandwidth Available Register
The initial bandwidth available register value is loaded into the corresponding bus-management CSR
register on a system (hardware) or software reset. See Table 8-19 for a complete description of the
register contents.
OHCI register offset: B0h
Register type: Read only, Read/Write
Default value: 0000 1333h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1
Table 8-19. Initial Bandwidth Available Register Description
BIT FIELD NAME TYPE DESCRIPTION
31-13 RSVD R Reserved. Bits 31-13 return 000 0000 0000 0000 0000b when read.
12-0 InitBWAvailable RW This field is reset to 1333h on a system (hardware) or software reset, and is not affected by a
1394 bus reset. The value of this field is loaded into the BANDWIDTH_AVAILABLE CSR
register upon a GRST, PERST, PRST, or 1394 bus reset.
154 1394 OHCI Memory-Mapped Register Space Copyright © 2008–2013, Texas Instruments Incorporated
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