Datasheet

XIO2213B

SCPS210F –OCTOBER 2008–REVISED MAY 2013

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8.23 Isochronous Transmit Interrupt Event Register

The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous

transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an

OUTPUT_LAST* command completes and its interrupt bits are set to 1. Upon determining that the

isochTx (bit 6) interrupt has occurred in the interrupt event register at OHCI offset 80h/84h (see

Section 8.21), software can check this register to determine which context caused the interrupt. The

interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal, or by writing a 1b in

the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1b

to the corresponding bit in the clear register. See Table 8-17 for a complete description of the register

contents.

OHCI register 90h set register

offset:

94h clear register (returns the contents of the isochronous transmit interrupt

event register bit-wise ANDed with the isochronous transmit interrupt

mask register when read)

Default value: 0000 00XXh

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 X X X X X X X X

Table 8-17. Isochronous Transmit Interrupt Event Register Description

BIT FIELD NAME TYPE DESCRIPTION

31-8 RSVD R Reserved. Bits 31-8 return 0000h when read.

7 isoXmit7 RSC Isochronous transmit context 7 caused the interrupt event register bit 6 (isochTx) interrupt.

6 isoXmit6 RSC Isochronous transmit context 6 caused the interrupt event register bit 6 (isochTx) interrupt.

5 isoXmit5 RSC Isochronous transmit context 5 caused the interrupt event register bit 6 (isochTx) interrupt.

4 isoXmit4 RSC Isochronous transmit context 4 caused the interrupt event register bit 6 (isochTx) interrupt.

3 isoXmit3 RSC Isochronous transmit context 3 caused the interrupt event register bit 6 (isochTx) interrupt.

2 isoXmit2 RSC Isochronous transmit context 2 caused the interrupt event register bit 6 (isochTx) interrupt.

1 isoXmit1 RSC Isochronous transmit context 1 caused the interrupt event register bit 6 (isochTx) interrupt.

0 isoXmit0 RSC Isochronous transmit context 0 caused the interrupt event register bit 6 (isochTx) interrupt.

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