Datasheet
XIO2213B
SCPS210F –OCTOBER 2008–REVISED MAY 2013
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Table 8-15. Interrupt Event Register Description (continued)
BIT FIELD NAME TYPE DESCRIPTION
5 RSPkt RSCU Indicates that a packet was sent to an asynchronous receive response context buffer and the
descriptor xferStatus and resCount fields have been updated
4 RQPkt RSCU Indicates that a packet was sent to an asynchronous receive request context buffer and the
descriptor xferStatus and resCount fields have been updated
3 ARRS RSCU Asynchronous receive response DMA interrupt. Bit 3 is conditionally set to 1b upon completion
of an ARRS DMA context command descriptor.
2 ARRQ RSCU Asynchronous receive request DMA interrupt. Bit 2 is conditionally set to 1b upon completion
of an ARRQ DMA context command descriptor.
1 respTxComplete RSCU Asynchronous response transmit DMA interrupt. Bit 1 is conditionally set to 1b upon
completion of an ATRS DMA command.
0 reqTxCompleter RSCU Asynchronous request transmit DMA interrupt. Bit 0 is conditionally set to 1b upon completion
of an ATRQ DMA command.
8.22 Interrupt Mask Register
The interrupt mask set/clear register enables the various interrupt sources. Reads from either the set
register or the clear register always return the contents of the interrupt mask register. In all cases except
masterIntEnable (bit 31) and vendorSpecific (bit 30), the enables for each interrupt event align with the
interrupt event register bits detailed in Table 8-15.
This register is fully compliant with the 1394 Open Host Controller Interface Specification, and the
controller adds an interrupt function to bit 30. See Table 8-16 for a complete description of bits 31 and 30.
OHCI register offset: 88h set register
8Ch clear register
Register type: Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read
only
Default value: XXXX 0XXXh
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE X X 0 0 0 X X X X X X X X 0 X X
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 X X X X X X X X X X
Table 8-16. Interrupt Mask Register Description
BIT FIELD NAME TYPE DESCRIPTION
31 masterIntEnable RSCU Master interrupt enable. If bit 31 is set to 1b, external interrupts are generated in accordance
with the interrupt mask register. If this bit is cleared, external interrupts are not generated,
regardless of the interrupt mask register settings.
30 VendorSpecific RSC When this bit and bit 30 (vendorSpecific) in the interrupt event register at OHCI offset 80h/84h
(see Section 8.21) are set to 11b, this vendor-specific interrupt mask enables interrupt
generation.
29 SoftInterrupt RSC When this bit and bit 29 (SoftInterrupt) in the interrupt event register at OHCI offset 80h/84h
(see Section 8.21) are set to 11b, this soft-interrupt mask enables interrupt generation.
28 RSVD R Reserved. Bit 28 returns 0b when read.
27 ack_tardy RSC When this bit and bit 27 (ack_tardy) in the interrupt event register at OHCI offset 80h/84h (see
Section 8.21) are set to 11b, this acknowledge-tardy interrupt mask enables interrupt
generation.
26 phyRegRcvd RSC When this bit and bit 26 (phyRegRcvd) in the interrupt event register at OHCI offset 80h/84h
(see Section 8.21) are set to 11b, this PHY register interrupt mask enables interrupt
generation.
25 cycleTooLong RSC When this bit and bit 25 (cycleTooLong) in the interrupt event register at OHCI offset 80h/84h
(see Section 8.21) are set to 11b, this cycle-too-long interrupt mask enables interrupt
generation.
150 1394 OHCI Memory-Mapped Register Space Copyright © 2008–2013, Texas Instruments Incorporated
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