Datasheet

XIO2213B
www.ti.com SCPS210F –OCTOBER 2008–REVISED MAY 2013
Table 8-15. Interrupt Event Register Description
BIT FIELD NAME TYPE DESCRIPTION
31 RSVD R Reserved. Bit 31returns 0b when read.
30 vendorSpecific RSC This vendor-specific interrupt event is reported when either of the general-purpose interrupts
are asserted. The general-purpose interrupts are enabled by setting the corresponding bits
INT_3EN and INT_2EN (bits 31 and 23, respectively) to 1 in the GPIO control register at offset
FCh in the PCI configuration space.
29 SoftInterrupt RSC Bit 29 is used by software to generate an interrupt for its own use.
28 RSVD R Reserved. Bit 28 returns 0b when read.
27 ack_tardy RSCU Bit 27 is set to 1b when bit 29 (AckTardyEnable) in the host controller control register at OHCI
offset 50h/54h (see Section 3.3.2) is set to 1b and any of the following conditions occur:
a. Data is present in a receive FIFO that is to be delivered to the host.
b. The physical response unit is busy processing requests or sending responses.
c. The controller sent an ack_tardy acknowledgment.
26 phyRegRcvd RSCU The controller has received a PHY register data byte that can be read from bits 23-16 in the
PHY control register at OHCI offset ECh (see Section 8.33).
25 cycleTooLong RSCU If bit 21 (cycleMaster) in the link control register at OHCI offset E0h/E4h (see Section 8.30) is
set to 1b, this indicates that over 125 s has elapsed between the start of sending a cycle start
packet and the end of a subaction gap. Bit 21 (cycleMaster) in the link control register is
cleared by this event.
24 unrecoverableError RSCU This event occurs when the controller encounters any error that forces it to stop operations on
any or all of its subunits, for example, when a DMA context sets its dead bit to 1b. While bit 24
is set to 1b, all normal interrupts for the context(s) that caused this interrupt are blocked from
being set to 1b.
23 cycleInconsistent RSCU A cycle start was received that had values for the cycleSeconds and cycleCount fields that are
different from the values in bits 31-25 (cycleSeconds field) and bits 24-12 (cycleCount field) in
the isochronous cycle timer register at OHCI offset F0h (see Section 8.34).
22 cycleLost RSCU A lost cycle is indicated when no cycle_start packet is sent or received between two
successive cycleSynch events. A lost cycle can be predicted when a cycle_start packet does
not immediately follow the first subaction gap after the cycleSynch event or if an arbitration
reset gap is detected after a cycleSynch event without an intervening cycle start. Bit 22 may
be set to 1b either when a lost cycle occurs or when logic predicts that one will occur.
21 cycle64Seconds RSCU Indicates that the seventh bit of the cycle second counter has changed
20 cycleSynch RSCU Indicates that a new isochronous cycle has started. Bit 20 is set to 1b when the low-order bit
of the cycle count toggles.
19 phy RSCU Indicates that the PHY requests an interrupt through a status transfer
18 regAccessFail RSCU Indicates that a register access has failed due to a missing SCLK clock signal from the PHY.
When a register access fails, bit 18 is set to 1b before the next register access.
17 busReset RSCU Indicates that the PHY has entered bus reset mode
16 selfIDcomplete RSCU A self-ID packet stream has been received. It is generated at the end of the bus initialization
process. Bit 16 is turned off simultaneously when bit 17 (busReset) is turned on.
15 selfIDcomplete2 RSCU Secondary indication of the end of a self-ID packet stream. Bit 15 is set to 1b by the controller
when it sets bit 16 (selfIDcomplete), and retains the state, independent of bit 17 (busReset).
14-10 RSVD R Reserved. Bits 14-10 return 00000b when read.
9 lockRespErr RSCU Indicates that the controller sent a lock response for a lock request to a serial bus register, but
did not receive an ack_complete
8 postedWriteErr RSCU Indicates that a host bus error occurred while the controller was trying to write a 1394 write
request, which had already been given an ack_complete, into system memory
7 isochRx RU Isochronous receive DMA interrupt. Indicates that one or more isochronous receive contexts
have generated an interrupt. This is not a latched event; it is the logical OR of all bits in the
isochronous receive interrupt event register at OHCI offset A0h/A4h (see Section 8.25) and
isochronous receive interrupt mask register at OHCI offset A8h/ACh (see Section 8.26). The
isochronous receive interrupt event register indicates which contexts have been interrupted.
6 isochTx RU Isochronous transmit DMA interrupt. Indicates that one or more isochronous transmit contexts
have generated an interrupt. This is not a latched event; it is the logical OR of all bits in the
isochronous transmit interrupt event register at OHCI offset 90h/94h (see Section 8.23) and
isochronous transmit interrupt mask register at OHCI offset 98h/9Ch (see Section 8.24). The
isochronous transmit interrupt event register indicates which contexts have been interrupted.
Copyright © 2008–2013, Texas Instruments Incorporated 1394 OHCI Memory-Mapped Register Space 149
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