Datasheet
XIO2213B
SCPS210F –OCTOBER 2008–REVISED MAY 2013
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8.20 Isochronous Receive Channel Mask Low Register
The isochronous receive channel mask low set/clear register enables packet receives from the lower 32
isochronous data channels. See Table 8-14 for a complete description of the register contents.
OHCI register offset: 78h set register
7Ch clear register
Register type: Read/Set/Clear
Default value: XXXX XXXXh
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE X X X X X X X X X X X X X X X X
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE X X X X X X X X X X X X X X X X
Table 8-14. Isochronous Receive Channel Mask Low Register Description
BIT FIELD NAME TYPE Description
31 isoChannel31 RSC When bit 31 is set to 1b, the controller is enabled to receive from isochronous channel number 31.
30 isoChannel30 RSC When bit 30 is set to 1b, the controller is enabled to receive from isochronous channel number 30.
29-2 isoChanneln RSC Bits 29-2 (isoChanneln, where n = 29, 28, 27, ..., 2) follow the same pattern as bits 31 and 30.
1 isoChannel1 RSC When bit 1 is set to 1b, the controller is enabled to receive from isochronous channel number 1.
0 isoChannel0 RSC When bit 0 is set to 1b, the controller is enabled to receive from isochronous channel number 0.
8.21 Interrupt Event Register
The interrupt event set/clear register reflects the state of the various interrupt sources. The interrupt bits
are set to 1b by an asserting edge of the corresponding interrupt signal or by writing a 1b in the
corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1b to
the corresponding bit in the clear register.
This register is fully compliant with the 1394 Open Host Controller Interface Specification, and the
controller adds a vendor-specific interrupt function to bit 30. When the interrupt event register is read, the
return value is the bit-wise AND function of the interrupt event and interrupt mask registers. See Table 8-
15 for a complete description of the register contents.
OHCI register offset: 80h set register
84h clear register [returns the content of the interrupt event register
bit-wise ANDed with the interrupt mask register when read]
Register type: Read/Set/Clear/Update, Read/Set/Clear, Read/Update, Read
only
Default value: XXXX 0XXXh
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 X 0 0 0 X X X X X X X X 0 X X
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 X X X X X X X X X X
148 1394 OHCI Memory-Mapped Register Space Copyright © 2008–2013, Texas Instruments Incorporated
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