Datasheet

XIO2213B

SCPS210F –OCTOBER 2008–REVISED MAY 2013

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To ensure that the XIO2213B conforms to IEEE Std 1394b-2002, the BMODE terminal must be asserted.

The BMODE terminal does not select the cable-interface mode of operation. BMODE selects the internal

PHY-section/LLC-section interface mode of operation and affects the arbitration modes on the cable.

BMODE must be pulled high during normal operation.

Three package terminals are used as inputs to set the default value for three configuration status bits in

the self-ID packet. They can be pulled high through a 1-kΩ resistor or hardwired low as a function of the

equipment design. The PC0, PC1, and PC2 terminals indicate the default power class status for the node

(the need for power from the cable or the ability to supply power to the cable). The contender bit in the

PHY register set indicates that the node is a contender either for the isochronous resource manager (IRM)

or for the bus manager (BM). On the XIO2213B, this bit can only be set by a write to the PHY register set.

If a node is to be a contender for IRM or BM, the node software must set this bit in the PHY register set.

2.1 Related Documents

• PCI Express™ to PCI/PCI-X Bridge Specification, Revision 1.0

• PCI Express™ Base Specification, Revision 1.1

• PCI Express™ Card Electromechanical Specification, Revision 1.1

• PCI Local Bus Specification, Revision 2.3 and Revision 3.0

• PCI-to-PCI Bridge Architecture Specification, Revision 1.1

• PCI Bus Power-Management Interface Specification, Revision 1.1 and Revision 1.2

• 1394 Open Host Controller Interface (OHCI) Specification, Release 1.2

• High-Performance Serial Bus, IEEE Std 1394-1995

• High-Performance Serial Bus, Amendment 1, IEEE Std 1394a-2000

• High-Performance Serial Bus, Amendment 2, IEEE Std 1394b-2002

• Express Card Standard, Release 1.0 and Release 1.1

• PCI Express™ Jitter and BER white paper

• PCI Mobile Design Guide, Revision 1.1

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