Datasheet

XIO2213B
www.ti.com SCPS210F –OCTOBER 2008–REVISED MAY 2013
8.9 Bus Options Register
The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 8-7 for a
complete description of the register contents.
OHCI register offset: 20h
Register type: Read/Write, Read only
Default value: 0000 B0X3h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 1 0 1 1 0 0 0 0 X X 0 0 0 0 1 1
Table 8-7. Bus Options Register Description
BIT FIELD NAME TYPE DESCRIPTION
31 irmc RW Isochronous resource-manager capable. IEEE Std 1394 bus-management field. Must be valid when
bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 3.3.2)
is set to 1b. The default value for this bit is 0b.
30 cmc RW Cycle master capable. IEEE Std 1394 bus-management field. Must be valid when bit 17 (linkEnable)
in the host controller control register at OHCI offset 50h/54h (see Section 3.3.2) is set to 1b. The
default value for this bit is 0b.
29 isc RW Isochronous support capable. IEEE Std 1394 bus-management field. Must be valid when bit 17
(linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 3.3.2) is set
to 1b. The default value for this bit is 0b.
28 bmc RW Bus manager capable. IEEE Std 1394 bus-management field. Must be valid when bit 17
(linkEnable) in the host controller control register at OHCI offset 50h/54h (see Section 3.3.2) is set
to 1b. The default value for this bit is 0b.
27 pmc RW Power-management capable. IEEE Std 1394 bus-management field. When bit 27 is set to 1b, this
indicates that the node is power-management capable. Must be valid when bit 17 (linkEnable) in the
host controller control register at OHCI offset 50h/54h (see Section 3.3.2) is set to 1b. The default
value for this bit is 0b.
26-24 RSVD R Reserved. Bits 26-24 return 000b when read.
23-16 cyc_clk_acc RW Cycle master clock accuracy (in parts per million). IEEE Std 1394 bus-management field. Must be
valid when bit 17 (linkEnable) in the host controller control register at OHCI offset 50h/54h (see
Section 3.3.2) is set to 1b. The default value for this field is 00h.
15-12
(1)
max_rec RW Maximum request. IEEE Std 1394 bus-management field. Hardware initializes this field to indicate
the maximum number of bytes in a block request packet that is supported by the implementation.
This value, max_rec_bytes, must be 512 or greater, and is calculated by 2^(max_rec + 1). Software
may change this field; however, this field must be valid at any time bit 17 (linkEnable) in the host
controller control register at OHCI offset 50h/54h (see Section 3.3.2) is set to 1b. A received block
write request packet with a length greater than max_rec_bytes may generate an ack_type_error.
This field is not affected by a software reset, and defaults to value indicating 4096 bytes on a
system (hardware) reset. The default value for this field is Bh.
11-8 RSVD R Reserved. Bits 11-8 return 0h when read.
7-6 g RW Generation counter. This field is incremented if any portion of the configuration ROM has been
incremented since the prior bus reset.
5-3 RSVD R Reserved. Bits 5-3 return 000b when read.
2-0 Lnk_spd R Link speed. This field returns 011b, indicating that the link speeds of 100M bit/s, 200M bit/s, 400M
bit/s, and 800M bit/s are supported.
(1) These bits are reset by PERST or FRST.
Copyright © 2008–2013, Texas Instruments Incorporated 1394 OHCI Memory-Mapped Register Space 139
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