Datasheet

XIO2213B
SCPS210F –OCTOBER 2008–REVISED MAY 2013 www.ti.com
8.3 Asynchronous Transmit Retries Register
The asynchronous transmit retries register indicates the number of times the controller attempts a retry for
asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See
Table 8-4 for a complete description of the register contents.
OHCI register offset: 08h
Register type: Read/Write, Read only
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 8-4. Asynchronous Transmit Retries Register Description
BIT FIELD NAME TYPE DESCRIPTION
31-29 secondLimit R The second limit field returns 000b when read, because outbound dual-phase retry is not
implemented.
28-16 cycleLimit R The cycle limit field returns 0 0000 0000 0000b when read, because outbound dual-
phase retry is not implemented.
15-12 RSVD R Reserved. Bits 15-12 return 0h when read.
11-8 maxPhysRespRetries RW This field tells the physical response unit how many times to attempt to retry the transmit
operation for the response packet when a busy acknowledge or ack_data_error is
received from the target node. The default value for this field is 0h.
7-4 maxATRespRetries RW This field tells the asynchronous transmit response unit how many times to attempt to
retry the transmit operation for the response packet when a busy acknowledge or
ack_data_error is received from the target node. The default value for this field is 0h.
3-0 maxATReqRetries RW This field tells the asynchronous transmit DMA request unit how many times to attempt
to retry the transmit operation for the response packet when a busy acknowledge or
ack_data_error is received from the target node. The default value for this field is 0h.
8.4 CSR Data Register
The CSR data register accesses the bus-management CSR registers from the host through compare-
swap operations. This register contains the data to be stored in a CSR if the compare is successful.
OHCI register offset: 0Ch
Register type: Read only
Default value: XXXX XXXXh
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE X X X X X X X X X X X X X X X X
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE X X X X X X X X X X X X X X X X
136 1394 OHCI Memory-Mapped Register Space Copyright © 2008–2013, Texas Instruments Incorporated
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