Datasheet
XIO2213B
SCPS210F –OCTOBER 2008–REVISED MAY 2013
www.ti.com
7.22 Link Enhancement Control Register
The link enhancement control register implements TI proprietary bits that are initialized by software or by a
serial EEPROM, if present. After these bits are set to 1b, their functionality is enabled only if bit 22
(aPhyEnhanceEnable) in the host controller control register at OHCI offset 50h/54h (see Section 3.3.2,
Host Controller Control Register) is set to 1. See Table 7-18 for a complete description of the register
contents.
PCI register offset: F4h
Register type: Read/Write, Read only
Default value: 0000 4000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
128 1394 OHCI PCI Configuration Space Copyright © 2008–2013, Texas Instruments Incorporated
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