Datasheet

XIO2213B
SCPS210F –OCTOBER 2008–REVISED MAY 2013 www.ti.com
7.17 Capability ID and Next Item Pointer Registers
The capability ID and next item pointer registers identify the linked-list capability item and provide a pointer
to the next capability item. See Table 7-13 for a complete description of the register contents.
PCI register offset: 44h
Register type: Read only
Default value: 0001h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Table 7-13. Capability ID and Next Item Pointer Registers Description
BIT FIELD NAME TYPE DESCRIPTION
15-8 NEXT_ITEM R Next item pointer. The OHCI controller supports only one additional capability that is communicated
to the system through the extended capabilities list; therefore, this field returns 00h when read.
7-0 CAPABILITY_ID R Capability identification. This field returns 01h when read, which is the unique ID assigned by the
PCI SIG for PCI power-management capability.
7.18 Power Management Capabilities Register
The power management capabilities register indicates the capabilities of the OHCI core related to PCI
power management. See Table 7-14 for a complete description of the register contents.
PCI register offset: 46h
Register type: Read only
Default value: 7E03h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1
Table 7-14. Power Management Capabilities Register Description
BIT FIELD NAME TYPE DESCRIPTION
15-11 PME_SUPPORT R PME support. This 5-bit field indicates the power states from which the OHCI core may assert PME.
This field returns a value of 01111b, indicating that PME is asserted from the D3hot, D2, D1, and D0
power states.
10 D2_SUPPORT R D2 support. Bit 10 is hardwired to 1b, indicating that the OHCI controller supports the D2 power state.
9 D1_SUPPORT R D1 support. Bit 9 is hardwired to 1b, indicating that the OHCI controller supports the D1 power state.
8-6 AUX_CURRENT R Auxiliary current. This 3-bit field reports the 3.3-V
AUX
auxiliary current requirements. This field returns
000b, because the 1394a core is not powered by V
AUX
.
5 DSI R Device-specific initialization. This bit returns 0b when read, indicating that the OHCI controller does
not require special initialization beyond the standard PCI configuration header before a generic class
driver is able to use it.
4 RSVD R Reserved. Bit 4 returns 0b when read.
3 PME_CLK R PME clock. This bit returns 0b when read, indicating that no host bus clock is required for the OHCI
controller to generate PME.
2-0 PM_VERSION R Power-management version. If bit 7 (PCI_PM_VERSION_CTRL) in the PCI miscellaneous
configuration register at offset F0h (see Section 7.21) is 0b, this field returns 010b indicating Revision
1.1 compatibility. If PCI_PM_VERSION_CTRL in the PCI miscellaneous configuration register is 1b,
this field returns 011b indicating Revision 1.2 compatibility.
124 1394 OHCI PCI Configuration Space Copyright © 2008–2013, Texas Instruments Incorporated
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