Datasheet

XIO2213B
www.ti.com SCPS210F –OCTOBER 2008–REVISED MAY 2013
7.15 Minimum Grant and Minimum Latency Registers
The minimum grant and minimum latency registers communicate to the system the desired setting of bits
15–8 in the latency timer and class cache line size register at offset 0Ch in the PCI configuration space
(see Section 7.6). If a serial EEPROM is detected, the contents of these registers are loaded through the
serial EEPROM interface. If no serial EEPROM is detected, these registers return a default value that
corresponds to the MAX_LAT = 4, MIN_GNT = 2. See Table 7-11 for a complete description of the
register contents.
PCI register offset: 3Eh
Register type: Read/Update
Default value: 0402h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0
Table 7-11. Minimum Grant and Minimum Latency Registers Description
BIT FIELD NAME TYPE DESCRIPTION
15-8
(1)
MAX_LAT RU Maximum latency. The contents of this field may be used by the host BIOS to assign an
arbitration priority level to the OHCI controller. The default for this register indicates that the
OHCI controller may access the PCI bus as often as every 0.25 s; thus, an extremely high
priority level is requested. Bits 11-8 of this field may also be loaded through the serial EEPROM.
7-0
(1)
MIN_GNT RU Minimum grant. The contents of this field may be used by the host BIOS to assign a latency timer
register value to the OHCI controller. The default for this register indicates that the OHCI
controller may sustain burst transfers for nearly 64 s and, thus, request a large value be
programmed in bits 15-8 of the OHCI controller latency timer and class cache line size register at
offset 0Ch in the PCI configuration space (see Section 7.6). Bits 3-0 of this field may also be
loaded through the serial EEPROM.
(1) These bits are reset by PERST or FRST.
7.16 OHCI Control Register
The PCI OHCI control register is defined by the 1394 Open Host Controller Interface Specification and
provides a bit for big endian PCI support. See Table 7-12 for a complete description of the register
contents.
PCI register offset: 40h
Register type: Read/Write, Read only
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 7-12. OHCI Control Register Description
BIT FIELD NAME TYPE DESCRIPTION
31-1 RSVD R Reserved. Bits 31-1 return 000 0000 0000 0000 0000 0000 0000 0000b when read.
0 GLOBAL_SWAP RW When bit 0 is set to 1b, all quadlets read from and written to the PCI interface are byte swapped (big
endian). The default value for this bit is 0b, which is little endian mode.
Copyright © 2008–2013, Texas Instruments Incorporated 1394 OHCI PCI Configuration Space 123
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