Datasheet

XIO2213B
www.ti.com SCPS210F –OCTOBER 2008–REVISED MAY 2013
7.4 Status Register
The status register provides status over the 1394b OHCI controller interface to the PCI bus. All bit
functions adhere to the definitions in the PCI Local Bus Specification, as shown in the following bit
descriptions. See Table 7-3 for a complete description of the register contents.
PCI register offset: 06h
Register type: Read/Clear/Update, Read only
Default value: 0230h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0
Table 7-3. Status Register Description
BIT FIELD NAME TYPE DESCRIPTION
15 PAR_ERR RCU Detected parity error. Bit 15 is set to 1b when either an address parity or data parity error is
detected.
14 SYS_ERR RCU Signaled system error. Bit 14 is set to 1b when PCI_SERR is enabled and the 1394b OHCI
controller has signaled a system error to the host.
13 MABORT RCU Received master abort. Bit 13 is set to 1b when a cycle initiated by the 1394b OHCI controller
on the PCI bus has been terminated by a master abort.
12 TABORT_REC RCU Received target abort. Bit 12 is set to 1b when a cycle initiated by the 1394b OHCI controller on
the PCI bus was terminated by a target abort.
11 TABORT_SIG RCU Signaled target abort. Bit 11 is set to 1b by the 1394b OHCI controller when it terminates a
transaction on the PCI bus with a target abort.
10-9 PCI_SPEEDO R DEVSEL timing. Bits 10 and 9 encode the timing of PCI_DEVSEL and are hardwired to 01b,
indicating that the 1394b OHCI controller asserts this signal at a medium speed on
nonconfiguration cycle accesses.
8 DATAPAR RCU Data parity error detected. Bit 8 is set to 1b when the following conditions have been met:
a. PCI_PERR was asserted by any PCI device including the OHCI controller.
b. 1394b OHCI controller was the bus master during the data parity error.
c. Bit 6 (PERR_EN) in the command register at offset 04h in the PCI configuration space
(see Section 7.3, Command Register) is set to 1b.
7 FBB_CAP R Fast back-to-back capable. The 1394b OHCI controller cannot accept fast back-to-back
transactions; therefore, bit 7 is hardwired to 0b.
6 UDF R User-definable features (UDFs) supported. The 1394b OHCI controller does not support the
UDF; therefore, bit 6 is hardwired to 0b.
5 66MHZ R 66-MHz capable. The 1394b OHCI controller operates at a maximum PCI_CLK frequency of 66
MHz; therefore, bit 5 is hardwired to 1b.
4 CAPLIST R Capabilities list. Bit 4 returns 1b when read, indicating that capabilities additional to standard
PCI are implemented. The linked list of PCI power-management capabilities is implemented in
this function.
3 INT_STATUS RU Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10
(INT_DISABLE) in the command register (PCI offset 04h, see Section 4.3) is a 0 and this bit is
a 1, is the functions INTx signal asserted. Setting the INT_DISABLE bit to a 1 has no effect on
the state of this bit. This bit has been defined as part of the PCI Local Bus Specification
(Revision 2.3).
2-0 RSVD R Reserved. Bits 3-0 return 0h when read.
Copyright © 2008–2013, Texas Instruments Incorporated 1394 OHCI PCI Configuration Space 117
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