Datasheet

XIO2213B
www.ti.com SCPS210F –OCTOBER 2008–REVISED MAY 2013
6.8 Serial-Bus Control and Status Register
The serial-bus control and status register is used to control the behavior of the serial-bus interface. This
register also provides status information about the state of the serial bus. This register is an alias for the
serial-bus control and status register in the PCI header.
Device control memory window register offset: 47h
Register type: Read only, Read/Write, Read/Clear
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Table 6-5. Serial-Bus Control and Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
7
(1)
PROT_SEL RW Protocol select. This bit selects the serial-bus address mode used.
0 = Slave address and word address are sent on the serial bus (default).
1 = Only the slave address is sent on the serial bus.
6 RSVD R Reserved. Returns 0b when read.
5 REQBUSY RU Requested serial-bus access busy. This bit is set when a software-initiated serial-bus cycle
is in progress.
0 = No serial-bus cycle
1 = Serial-bus cycle in progresss
4
(1)
ROMBUSY RU Serial EEPROM access busy. This bit is set when the serial EEPROM circuitry in the
bridge is downloading register defaults from a serial EEPROM.
0 = No EEPROM activity
1 = EEPROM download in progress
3
(1)
SBDETECT RWU Serial EEPROM detected. This bit enables the serial-bus interface. The value of this bit
controls whether the GPIO4/SCL and GPIO5/SDA terminals are configured as GPIO
signals or as serial-bus signals. This bit is automatically set to 1b when a serial EEPROM
is detected.
Note: A serial EEPROM is only detected once following PERST.
0 = No EEPROM present, EEPROM load process does not happen. GPIO4//SCL and
GPIO5//SDA terminals are configured as GPIO signals.
1 = EEPROM present, EEPROM load process takes place. GPIO4/SCL and
GPIO5/SDA terminals are configured as serial-bus signals.
2
(1)
SBTEST RW Serial-bus test. This bit is used for internal test purposes. This bit controls the clock source
for the serial interface clock.
0 = Serial-bus clock at normal operating frequency ~60 kHz (default)
1 = Serial-bus clock frequency increased for test purposes ~4 MHz
1
(1)
SB_ERR RCU Serial-bus error. This bit is set when an error occurs during a software-initiated serial-bus
cycle.
0 = No error
1 = Serial-bus error
0
(1)
ROM_ERR RCU Serial EEPROM load error. This bit is set when an error occurs while downloading
registers from a serial EEPROM.
0 = No error
1 = EEPROM load error
(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.
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