Datasheet

XIO2213B
www.ti.com SCPS210F –OCTOBER 2008–REVISED MAY 2013
6 Memory-Mapped TI Proprietary Register Space
The programming model of the memory-mapped TI proprietary register space is unique to this device.
These custom registers are specifically designed to provide enhanced features associated with upstream
isochronous applications.
Sticky bits are reset by a fundamental reset (FRST).
Table 6-1. Device Control Memory Window Register Map
REGISTER NAME OFFSET
Reserved Revision ID Device control map ID 00h
Reserved 04h-3Ch
GPIO data
(1)
GPIO control
(1)
40h
Serial-bus control and status
(1)
Serial-bus slave address
(1)
Serial-bus word address
(1)
Serial-bus data
(1)
44h
(1) This register shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.
6.1 Device Control Map ID Register
The device control map ID register identifies the TI proprietary layout for this device control map. The
value 04h identifies this as a PCIe-to-PCI bridge without isochronous capabilities.
Device control memory window register 00h
offset:
Register type: Read only
Default value: 04h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 1 0 0
Copyright © 2008–2013, Texas Instruments Incorporated Memory-Mapped TI Proprietary Register Space 109
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