Datasheet
XIO2213B
SCPS210F –OCTOBER 2008–REVISED MAY 2013
www.ti.com
5.10 Secondary Uncorrectable Error Status Register
The secondary uncorrectable error status register reports the status of individual PCI bus errors as they
occur. Software may only clear these bits by writing a 1b to the desired location. See Table 5-8 for a
complete description of the register contents.
PCIe extended register offset: 12Ch
Register type: Read only, Read/Clear
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 5-8. Secondary Uncorrectable Error Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:13 RSVD R Reserved. Returns 000 0000 0000 0000 0000b when read.
12
(1)
SERR_DETECT RCU SERR assertion detected. This bit is asserted when the bridge detects the assertion of
SERR on the secondary bus.
11
(1)
PERR_DETECT RCU PERR assertion detected. This bit is asserted when the bridge detects the assertion of
PERR on the secondary bus.
10
(1)
DISCARD_TIMER RCU Delayed transaction discard timer expired. This bit is asserted when the discard timer
expires for a pending delayed transaction that was initiated on the secondary bus.
9
(1)
UNCOR_ADDR RCU Uncorrectable address error. This bit is asserted when the bridge detects a parity error
during the address phase of an upstream transaction.
8 RSVD R Reserved. Returns 0b when read.
7
(1)
UNCOR_DATA RCU Uncorrectable data error. This bit is asserted when the bridge detects a parity error during
a data phase of an upstream write transaction, or when the bridge detects the assertion of
PERR when forwarding read completion data to a PCI device.
6:4 RSVD R Reserved. Returns 000b when read.
3
(1)
MASTER_ABORT RCU Received master abort. This bit is asserted when the bridge receives a master abort on
the PCI interface.
2
(1)
TARGET_ABORT RCU Received target abort. This bit is asserted when the bridge receives a target abort on the
PCI interface.
1:0 RSVD R Reserved. Returns 00b when read.
(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.
104 PCIe Extended Configuration Space Copyright © 2008–2013, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: XIO2213B