Datasheet

XIO2213B
www.ti.com SCPS210F –OCTOBER 2008–REVISED MAY 2013
5.6 Correctable Error Status Register
The correctable error status register reports the status of individual errors as they occur. Software may
only clear these bits by writing a 1b to the desired location. See Table 5-5 for a complete description of
the register contents.t
PCIe extended register 110h
offset:
Register type: Read only, Read/Clear
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 5-5. Correctable Error Status Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:14 RSVD R Reserved. Returns 000 0000 0000 0000 0000b when read.
13 ANFES RCU Advisory nonfatal error status. This bit is asserted when an advisory nonfatal error has been
reported.
12
(1)
REPLAY_TMOUT RCU Replay timer time-out. This bit is asserted when the replay timer expires for a pending request
or completion that has not been acknowledged.
11:9 RSVD R Reserved. Returns 000b when read.
8
(1)
REPLAY_ROLL RCU REPLAY_NUM rollover. This bit is asserted when the replay counter rolls over after a pending
request or completion has not been acknowledged.
7
(1)
BAD_DLLP RCU Bad DLLP error. This bit is asserted when an 8b/10b error was detected by the PHY during
the reception of a DLLP.
6
(1)
BAD_TLP RCU Bad TLP error. This bit is asserted when an 8b/10b error was detected by the PHY during the
reception of a TLP.
5:1 RSVD R Reserved. Returns 00000b when read.
0
(1)
RX_ERROR RCU Receiver error. This bit is asserted when an 8b/10b error is detected by the PHY at any time.
(1) These bits shall only be reset by a fundamental reset (FRST). FRST is asserted (low) whenever PERST or GRST is asserted.
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