Datasheet
PCI Express Extended Configuration Space
86
March 5 2007 − June 2011SCPS154C
5.8 Advanced Error Capabilities and Control Register
The advanced error capabilities and control register allows the system to monitor and control the advanced
error reporting capabilities. See Table 5−7 for a complete description of the register contents.
PCI Express extended register offset: 118h
Register type: Read-only, Read/Write
Default value: 0000 00A0h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
Table 5−7. Advanced Error Capabilities and Control Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:9 RSVD R Reserved. Returns 000 0000 0000 0000 0000 0000b when read.
8† ECRC_CHK_EN RW
Extended CRC check enable
0 = Extended CRC checking is disabled
1 = Extended CRC checking is enabled
7 ECRC_CHK_CAPABLE R
Extended CRC check capable. This read-only bit returns a value of 1b indicating that the
bridge is capable of checking extended CRC information.
6† ECRC_GEN_EN RW
Extended CRC generation enable
0 = Extended CRC generation is disabled
1 = Extended CRC generation is enabled
5 ECRC_GEN_CAPABLE R
Extended CRC generation capable. This read-only bit returns a value of 1b indicating that
the bridge is capable of generating extended CRC information.
4:0† FIRST_ERR RU
First error pointer. This 5-bit value reflects the bit position within the uncorrectable error
status register (offset 104h, see Section 5.3) corresponding to the class of the first error
condition that was detected.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
5.9 Header Log Register
The header log register stores the TLP header for the packet that lead to the most recently detected error
condition. Offset 11Ch contains the first DWORD. Offset 128h contains the last DWORD (in the case of a 4DW
TLP header). Each DWORD is stored with the least significant byte representing the earliest transmitted.
These bits are reset by a PCI Express reset (PERST
), a GRST, or the internally-generated power-on reset.
PCI Express extended register offset: 11Ch, 120h, 124h, and 128h
Register type: Read-only
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Not Recommended for New Designs