Datasheet

PCI Express Extended Configuration Space

March 5 2007 − June 2011 SCPS154C

5.3 Uncorrectable Error Status Register

The uncorrectable error status register reports the status of individual errors as they occur on the primary PCI

Express interface. Software may only clear these bits by writing a 1b to the desired location. See Table 5−2

for a complete description of the register contents.

PCI Express extended register offset: 104h

Default value: 0000h

BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 5−2. Uncorrectable Error Status Register Description

BIT FIELD NAME ACCESS DESCRIPTION

31:21 RSVD R Reserved. Returns 000 0000 0000b when read.

20† UR_ERROR RCU Unsupported request error. This bit is asserted when an unsupported request is received.

19† ECRC_ERROR RCU Extended CRC error. This bit is asserted when an extended CRC error is detected.

18† MAL_TLP RCU Malformed TLP. This bit is asserted when a malformed TLP is detected.

17† RX_OVERFLOW RCU

Receiver overflow. This bit is asserted when the flow control logic detects that the transmitting

device has illegally exceeded the number of credits that were issued.

16† UNXP_CPL RCU

Unexpected completion. This bit is asserted when a completion packet is received that does

not correspond to an issued request.

15† CPL_ABORT RCU Completer abort. This bit is asserted when the bridge signals a completer abort.

14† CPL_TIMEOUT RCU

Completion time-out. This bit is asserted when no completion has been received for an issued

request before the time-out period.

13† FC_ERROR RCU

Flow control error. This bit is asserted when a flow control protocol error is detected either

during initialization or during normal operation.

12† PSN_TLP RCU Poisoned TLP. This bit is asserted when a poisoned TLP is received.

11:5 RSVD R Reserved. Returns 000 0000b when read.

4† DLL_ERROR RCU Data link protocol error. This bit is asserted if a data link layer protocol error is detected.

3:0 RSVD R Reserved. Returns 0h when read.

†

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

Not Recommended for New Designs