Datasheet

PCI Express Extended Configuration Space
80
March 5 2007 − June 2011SCPS154C
Table 5−1. PCI Express Extended Configuration Register Map (Continued)
REGISTER NAME OFFSET
VC arbitration table (phase 31 − phase 24) 18Ch
Reserved 190h – 1BCh
Port arbitration table for VC1 (phase 7 – phase 0) 1C0h
Port arbitration table for VC1 (phase 15 – phase 8) 1C4h
Port arbitration table for VC1 (phase 23 – phase 16) 1C8h
Port arbitration table for VC1 (phase 31 – phase 24) 1CCh
Port arbitration table for VC1 (phase 39 – phase 32) 1D0h
Port arbitration table for VC1 (phase 47 – phase 40) 1D4h
Port arbitration table for VC1 (phase 55 – phase 48) 1D8h
Port arbitration table for VC1 (phase 63 – phase 56) 1DCh
Port arbitration table for VC1 (phase 71 – phase 64) 1E0h
Port arbitration table for VC1 (phase 79 – phase 72) 1E4h
Port arbitration table for VC1 (phase 87 – phase 80) 1E8h
Port arbitration table for VC1 (phase 95 – phase 88) 1ECh
Port arbitration table for VC1 (phase 103 – phase 96) 1F0h
Port arbitration table for VC1 (phase 111 – phase 104) 1F4h
Port arbitration table for VC1 (phase 119 – phase 112) 1F8h
Port arbitration table for VC1 (phase 127 – phase 120) 1FCh
Reserved 200h – FFCh
†
One or more bits in this register are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
5.1 Advanced Error Reporting Capability ID Register
This read-only register identifies the linked list item as the register for PCI Express advanced error reporting
capabilities. The register returns 0001h when read.
PCI Express extended register offset: 100h
Register type: Read-only
Default value: 0001h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
5.2 Next Capability Offset/Capability Version Register
This read-only register identifies the next location in the PCI Express extended capabilities link list. If bit 12
(VC_CAP_EN) in the general control register (offset D4h, see Section 4.65) is 0b, then the upper 12 bits in
this register are 000h, indicating the end of the linked list. If VC_CAP_EN is 1b, then the upper 12 bits in this
register are 150h, indicating the existance of the VC capability structure at offset 150h. The four least
significant bits identify the revision of the current capability block as 1h.
PCI Express extended register offset: 102h
Register type: Read-only
Default value: XX01h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 x 0 x 0 x 0 0 0 0 0 0 0 1
Not Recommended for New Designs