Datasheet

Classic PCI Configuration Space

March 5 2007 − June 2011SCPS154C

4.69 Arbiter Control Register

The arbiter control register controls the bridge internal arbiter. The arbitration scheme used is a two-tier

rotational arbitration. The bridge is the only secondary bus master that defaults to the higher priority arbitration

tier. See Table 4−40 for a complete description of the register contents.

PCI register offset: DCh

Default value: 40h

BIT NUMBER 7 6 5 4 3 2 1 0

RESET STATE 0 1 0 0 0 0 0 0

Table 4−40. Arbiter Control Register Description

BIT FIELD NAME ACCESS DESCRIPTION

7† PARK RW

Bus parking mode. This bit determines where the internal arbiter parks the secondary bus.

When this bit is set, the arbiter parks the secondary bus on the bridge. When this bit is

cleared, the arbiter parks the bus on the last device mastering the secondary bus.

0 = Park the secondary bus on the last secondary bus master (default)

1 = Park the secondary bus on the bridge

6† BRIDGE_TIER_SEL RW

Bridge tier select. This bit determines in which tier the bridge is placed in the arbitration

scheme.

0 = Lowest priority tier

1 = Highest priority tier (default)

5:1† RSVD RW

Reserved. These bits are reserved and must not be changed from their default value of

00000b.

0† OHCI_TIER_SEL RW

1394a OHCI tier select. This bit determines in which tier the 1394a OHCI is placed in the

arbitration scheme.

0 = Lowest priority tier (default)

1 = Highest priority tier

†

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

Not Recommended for New Designs