Datasheet

Classic PCI Configuration Space
75
March 5 2007 − June 2011 SCPS154C
4.66 TI Proprietary Register
This read/write TI proprietary register is located at offset D8h and controls TI proprietary functions. This
register must not be changed from the specified default state. This register is reset by a PCI Express reset
(PERST
), a GRST, or the internally-generated power-on reset.
PCI register offset: D8h
Register type: Read-only, Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
4.67 TI Proprietary Register
This read/write TI proprietary register is located at offset D9h and controls TI proprietary functions. This
register must not be changed from the specified default state. This register is reset by a PCI Express reset
(PERST
), a GRST, or the internally-generated power-on reset.
PCI register offset: D9h
Register type: Read-only, Read/Write
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
4.68 TI Proprietary Register
This read-only TI proprietary register is located at offset DAh and controls TI proprietary functions. This
register must not be changed from the specified default state. This register is reset by a PCI Express reset
(PERST
), a GRST, or the internally-generated power-on reset.
PCI register offset: DAh
Register type: Read-only
Default value: 00h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0
Not Recommended for New Designs