Datasheet

Classic PCI Configuration Space
74
March 5 2007 − June 2011SCPS154C
Table 4−39. General Control Register Description (Continued)
BIT FIELD NAME ACCESS DESCRIPTION
19†
READ_
PREFETCH_
DIS
RW
Read prefetch disable. This bit controls the prefetch functionality on PCI memory read
transactions.
0 = Prefetch to the next cache line boundary on a burst read (default)
1 = Fetch only a single DWORD on a burst read
18:16† L0s_LATENCY RW
L0s maximum exit latency. This field programs the maximum acceptable latency when exiting the
L0s state. This sets bits 8:6 (EP_L0S_LAT) in the device capabilities register (offset 94h, see
Section 4.49).
000 = Less than 64 ns
001 = 64 ns up to less than 128 ns
010 = 128 ns up to less than 256 ns
011 = 256 ns up to less than 512 ns
100 = 512 ns up to less than 1 μs
101 = 1 μs up to less than 2 μs
110 = 2 μs to 4 μs (default)
111 = More than 4 μs
15:13† L1_LATENCY RW
L1 maximum exit latency. This field programs the maximum acceptable latency when exiting the L1
state. This sets bits 11:9 (EP_L1_LAT) in the device capabilities register (offset 94h, see
Section 4.49).
000 = Less than 1 μs
001 = 1 μs up to less than 2 μs
010 = 2 μs up to less than 4 μs
011 = 4 μs up to less than 8 μs
100 = 8 μs up to less than 16 μs
101 = 16 μs up to less than 32 μs
110 = 32 μs to 64 μs (default)
111 = More than 64 μs
12† VC_CAP_EN RW
VC capability structure enable. This bit enables the VC capability structure by changing the next
offset field of the advanced error reporting capability register at offset 102h.
0 = VC capability structure disabled (offset field = 000h)
1 = VC capability structure enabled (offset field = 150h)
11
k
BPCC_E RW
Bus power clock control enable. This bit controls whether the secondary bus PCI clocks are
stopped when the bridge is placed in the D3 state. It is assumed that if the secondary bus clocks
are required to be active, that a reference clock continues to be provided on the PCI Express
interface.
0 = Secondary bus clocks are not stopped in D3 (default)
1 = Secondary bus clocks are stopped on D3
10
k
BEACON_
ENABLE
RW
Beacon enable. This bit controls the mechanism for waking up the physical PCI Express link when
in L2.
0 = WAKE
mechanism is used exclusively. Beacon is not used (default)
1 = Beacon and WAKE
mechanisms are used
9:8†
MIN_POWER_
SCALE
RW
Minimum power scale. This value is programmed to indicate the scale of bits 7:0
(MIN_POWER_VALUE).
00 = 1.0x (default)
01 = 0.1x
10 = 0.01x
11 = 0.001x
7:0†
MIN_POWER_
VALUE
RW
Minimum power value. This value is programmed to indicate the minimum power requirements.
This value is multiplied by the minimum power scale field (bits 9:8) to determine the minimum
power requirements for the bridge. The default is 00h, because this feature is only usable when the
system implementer adds the PCI devices’ power consumption to the bridge power consumption
and reprograms this field with an EEPROM or the system BIOS.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
kThese bits are sticky and must retain their value when the bridge is powered by V
AUX
.
Not Recommended for New Designs