Datasheet

Classic PCI Configuration Space
73
March 5 2007 − June 2011 SCPS154C
4.65 General Control Register
This read/write register controls various functions of the bridge. See Table 4−39 for a complete description
of the register contents.
PCI register offset: D4h
Register type: Read-only, Read/Write
Default value: 8206 C000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−39. General Control Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:30†
CFG_RETRY
_CNTR
RW
Configuration retry counter. Configures the amount of time that a configuration request must be retried
on the secondary PCI bus before it may be completed with configuration retry status on the PCI
Express side.
00 = 25 μs
01 = 1 ms
10 = 25 ms (default)
11 = 50 ms
29:28 RSVD R Reserved. Returns 00b when read.
27†
LOW_POWER
_EN
RW
Low-power enable. When this bit is set, the half-ampitude, no preemphasis mode for the PCI Express
TX drivers is enabled. The default for this bit is 0b.
26†
PCI_PM_
VERSION_
CTRL
RW
PCI power management version control. This bit controls the value reported in bits 2:0 (PM_VERSION)
in the power management capabilities register (offset 52h, see Section 4.32). It also controls the value
of bit 3 (NO_SOFT_RESET) in the power management control/status register (offset 54h, see Section
4.33).
0 = Version fields reports 010b and NO_SOFT_RESET reports 0b for Power Management 1.1
compliance (default)
1 = Version fields reports 011b and NO_SOFT_RESET reports 1b for Power Management 1.2
compliance
25†
STRICT_
PRIORITY_EN
RW
Strict priority enable. When this bit is set and bits 6:4 (LOW_PRIORITY_COUNT) in the port VC
capability register 1 (offset 154h, see Section 5.17) are 000b, meaning that strict priority VC arbitration
is used, the extended VC always receives priority over VC0 at the PCI Express port.
0 = The default LOW_PRIORITY_COUNT is 001b
1 = The default LOW_PRIORITY_COUNT is 000b (default)
24† FORCE_MRM RW
Force memory read multiple
0 = Memory read multiple transactions are disabled (default)
1 = All upstream memory read transactions initiated on the PCI bus are treated as though they
are memory read multiple transactions where prefetching is supported
23†
ASPM_CTRL_
DEF_OVRD
RW
Active state power management control default override. This bit determines the power-up default for
bits 1:0 (ASLPMC) of the link control register (offset A0h, see Section 4.53) in the PCI Express
capability structure.
0 = Power-on default indicates that active state power management is disabled (00b) (default)
1 = Power-on default indicates that active state power management is enabled for L0s and L1 (11b)
22:20†
POWER_
OVRD
RW
Power override. This bit field determines how the bridge responds when the slot power limit is less
than the amount of power required by the bridge and the devices behind the bridge.
000 = Ignore slot power limit (default).
001 = Assert the PWR_OVRD terminal.
010 = Disable secondary clocks selected by the clock mask register.
011 = Disable secondary clocks selected by the clock mask register and assert the PWR_OVRD
terminal.
100 = Respond with unsupported request to all transactions except for configuration transactions
(type 0 or type 1) and set slot power limit messages.
101, 110, 111 = Reserved
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Not Recommended for New Designs