Datasheet

Classic PCI Configuration Space
71
March 5 2007 − June 2011 SCPS154C
4.62 Control and Diagnostic Register 1
The contents of this register are used for monitoring status and controlling behavior of the bridge. See
Table 4−36 for a complete description of the register contents. It is recommended that all values within this
register be left at the default value. Improperly programming fields in this register may cause interoperability
or other problems.
PCI register offset: C4h
Register type: Read/Write
Default value: 0012 0108h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0
Table 4−36. Control and Diagnostic Register 1 Description
BIT FIELD NAME ACCESS DESCRIPTION
32:21 RSVD R Reserved. Returns 000h when read.
20:18†
L1_EXIT_LAT_
ASYNC
RW
L1 exit latency for asynchronous clock. When bit 6 (CCC) of the link control register (offset A0h,
see Section 4.53) is set, the value in this field is mirrored in bits 17:15 (L1_LATENCY) field in the
link capabilities register (offset 9Ch, see Section 4.52). This field defaults to 100b.
17:15†
L1_EXIT_LAT_
COMMON
RW
L1 exit latency for common clock. When bit 6 (CCC) of the link control register (offset A0h, see
Section 4.53) is clear, the value in this field is mirrored in bits 17:15 (L1_LATENCY) field in the link
capabilities register (offset 9Ch, see Section 4.52). This field defaults to 100b.
14:11† RSVD RW
Reserved. Bits 14:11 default to 0000b. If this register is programmed via EEPROM or another
mechanism, the value written into this field must be 0000b.
10†
SBUS_RESET
_MASK
RW
Secondary bus reset bit mask. When this bit is set, the bridge masks the reset caused by bit 6
(SRST) of the bridge control register (offset 3Eh, see Section 4.29). This bit defaults to 0b.
9:6†
L1ASPM_
TIMER
RW
L1ASPM entry timer. This field specifies the value (in 512-ns ticks) of the L1ASPM entry timer. This
field defaults to 0100b.
5:2† L0s_TIMER RW
L0s entry timer. This field specifies the value (in 62.5-MHz clock ticks) of the L0s entry timer. This
field defaults to 0010b.
1:0† RSVD RW
Reserved. Bits 1:0 default to 00b. If this register is programmed via EEPROM or another
mechanism, then the value written into this field must be 00b.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Not Recommended for New Designs