Datasheet

Classic PCI Configuration Space
69
March 5 2007 − June 2011 SCPS154C
4.60 GPIO Data Register
This register reads the state of the input mode GPIO terminals and changes the state of the output mode GPIO
terminals. Writing to a bit that is in input mode or is enabled for a secondary function is ignored. The secondary
functions share GPIO4 (SCL) and GPIO5 (SDA). The default value at power up depends on the state of the
GPIO terminals as they default to general-purpose inputs. See Table 4−34 for a complete description of the
register contents.
PCI register offset: B6h
Register type: Read-only, Read/Write
Default value: 00XXh
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 x x x x x x x x
Table 4−34. GPIO Data Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:8 RSVD R Reserved
7† GPIO7_DATA RW
GPIO 7 data. This bit reads the state of GPIO7 when in input mode or changes the state of GPIO7
when in output mode.
6† GPIO6_DATA RW
GPIO 6 data. This bit reads the state of GPIO6 when in input mode or changes the state of GPIO6
when in output mode.
5† GPIO5_DATA RW
GPIO 5 data. This bit reads the state of GPIO5 when in input mode or changes the state of GPIO5
when in output mode.
4† GPIO4_DATA RW
GPIO 4 data. This bit reads the state of GPIO4 when in input mode or changes the state of GPIO4
when in output mode.
3† GPIO3_DATA RW
GPIO 3 data. This bit reads the state of GPIO3 when in input mode or changes the state of GPIO3
when in output mode.
2† GPIO2_DATA RW
GPIO 2 data. This bit reads the state of GPIO2 when in input mode or changes the state of GPIO2
when in output mode.
1† GPIO1_DATA RW
GPIO 1 data. This bit reads the state of GPIO1 when in input mode or changes the state of GPIO1
when in output mode.
0† GPIO0_DATA RW
GPIO 0 data. This bit reads the state of GPIO0 when in input mode or changes the state of GPIO0
when in output mode.
†
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Not Recommended for New Designs