Datasheet

Classic PCI Configuration Space

March 5 2007 − June 2011SCPS154C

4.53 Link Control Register

The link control register controls link specific behavior. See Table 4−29 for a complete description of the

PCI register offset: A0h

Default value: 0000h

BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Table 4−29. Link Control Register Description

BIT FIELD NAME ACCESS DESCRIPTION

15:8 RSVD RW Reserved. Returns 00h when read.

7 ES RW

Extended synch. This bit forces the bridge to extend the transmission of FTS ordered sets and an

extra TS2 when exiting from L1 prior to entering to L0.

0 = Normal synch (default)

1 = Extended synch

6 CCC RW

Common clock configuration. When this bit is set, it indicates that the bridge and the device at the

opposite end of the link are operating with a common clock source. A value of 0b indicates that the

bridge and the device at the opposite end of the link are operating with separate reference clock

sources. The bridge uses this common clock configuration information to report the correct L0s and

L1 exit latencies.

0 = Reference clock is asynchronous (default)

1 = Reference clock is common

5 RL R Retrain link. This bit has no function and is read-only 0b.

4 LD R Link disable. This bit has no function and is read-only 0b.

3 RCB RW

Read completion boundary. This bit is an indication of the RCB of the root complex. The state of

this bit has no affect on the bridge, since the RCB of the bridge is fixed at 128 bytes.

0 = 64 bytes (default)

1 = 128 bytes

2 RSVD R Reserved. Returns 0b when read.

1:0 ASLPMC RW

Active state link PM control. This field enables and disables the active state PM.

00 = Active state PM disabled (default)

01 = L0s entry enabled

10 = L1 entry enabled

11 = L0s and L1 entry enabled

Not Recommended for New Designs