Datasheet

Classic PCI Configuration Space
58
March 5 2007 − June 2011SCPS154C
4.43 Next Item Pointer Register
The contents of this read-only register indicate the next item in the linked list of capabilities for the bridge. This
register reads 90h pointing to the PCI Express capabilities registers.
PCI register offset: 81h
Register type: Read-only
Default value: 90h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 1 0 0 1 0 0 0 0
4.44 Subsystem Vendor ID Register
This register, used for system and option card identification purposes, may be required for certain operating
systems. This read-only register is initialized through the EEPROM and can be written through the subsystem
alias register. This register is reset by a PCI Express reset (PERST
), a GRST, or the internally-generated
power-on reset.
PCI register offset: 84h
Register type: Read-only
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.45 Subsystem ID Register
This register, used for system and option card identification purposes, may be required for certain operating
systems. This read-only register is initialized through the EEPROM and can be written through the subsystem
alias register. This register is reset by a PCI Express reset (PERST
), a GRST, or the internally-generated
power-on reset.
PCI register offset: 86h
Register type: Read-only
Default value: 0000h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
4.46 PCI Express Capability ID Register
This read-only register identifies the linked list item as the register for PCI Express capabilities. The register
returns 10h when read.
PCI register offset: 90h
Register type: Read-only
Default value: 10h
BIT NUMBER 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 1 0 0 0 0
Not Recommended for New Designs