Datasheet
Classic PCI Configuration Space
56
March 5 2007 − June 2011SCPS154C
4.38 MSI Message Control Register
This register controls the sending of MSI messages. See Table 4−21 for a complete description of the register
contents.
PCI register offset: 62h
Register type: Read-only, Read/Write
Default value: 0088h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0
Table 4−21. MSI Message Control Register Description
BIT FIELD NAME ACCESS DESCRIPTION
15:8 RSVD R Reserved. Returns 00h when read.
7 64CAP R
64-bit message capability. This bit is read-only 1b indicating that the bridge supports 64-bit MSI
message addressing.
6:4 MM_EN RW
Multiple message enable. This bit indicates the number of distinct messages that the bridge is
allowed to generate.
000 = 1 message (default)
001 = 2 messages
010 = 4 messages
011 = 8 messages
100 = 16 messages
101 = Reserved
110 = Reserved
111 = Reserved
3:1 MM_CAP R
Multiple message capabilities. This field indicates the number of distinct messages that bridge is
capable of generating. This field is read-only 100b indicating that the bridge can signal 1 interrupt
for each IRQ supported on the serial IRQ stream up to a maximum of 16 unique interrupts.
0 MSI_EN RW
MSI enable. This bit enables MSI interrupt signaling. MSI signaling must be enabled by software
for the bridge to signal that a serial IRQ has been detected.
0 = MSI signaling is prohibited (default)
1 = MSI signaling is enabled
NOTE: Enabling MSI messaging in the XIO2200A has no effect.
4.39 MSI Message Lower Address Register
This register contains the lower 32 bits of the address that a MSI message writes to when a serial IRQ is
detected. See Table 4−22 for a complete description of the register contents.
PCI register offset: 64h
Register type: Read-only, Read/Write
Default value: 0000 0000h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESET STATE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4−22. MSI Message Lower Address Register Description
BIT FIELD NAME ACCESS DESCRIPTION
31:2 ADDRESS RW System specified message address
1:0 RSVD R Reserved. Returns 00b when read.
NOTE: Enabling MSI messaging in the XIO2200A has no effect.
Not Recommended for New Designs